Intel 80386 manual Base Architecture Introduction, Register Overview

80386

2.BASE ARCHITECTURE

2.1INTRODUCTION

The B03B6 consists of a central processing unit, a memory management unit and a bus interface.

The central processing unit consists of the execu- tion unit and instruction unit. The execution unit con- tains the eight 32-bit general purpose registers which are used for both address calculation, data operations and a 64-bit barrel shifter used to speed shift, rotate, multiply, and divide operations. The multiply and divide logic uses a 1-bit per cycle algo- rithm. The multiply algorithm stops the iteration when the most significant bits of the multiplier are all zero. This allows typical 32-bit multiplies to be exe- cuted in under one microsecond. The instruction unit decodes the instruction opcodes and stores them in the decoded instruction queue for immediate use by the execution unit.

The memory management unit (MMU) consists of a segmentation unit and a paging unit. Segmentation allows the managing of the logical address space by providing an extra addressing component, one that allows easy code and data relocatability, and effi- cient sharing. The paging mechanism operates be- neath and is transparent to the segmentation proc- ess, to allow management of the physical address space. Each segment is divided into one or more 4K byte pages. To implement a virtual memory system, the B03B6 supports full restartability for all page and segment faults.

Memory is organized into one or more variable length segments, each up to four gigabytes in size. A given region of the linear address space, a segment, can have attributes associated with it. These attri- butes include its location, size, type (Le. stack, code or data), and protection characteristics. Each task on an B03B6 can have a maximum of 16,3B1 seg- ments of up to four gigabytes each, thus providing 64 terabytes (trillion bytes) of virtual memory to each task.

The segmentation unit provides four-levels of pro- tection for isolating and protecting applications and the operating system from each other. The hardware enforced protection allows the design of systems with a high degree of integrity.

The 80386 has two modes of operation: Real Ad- dress Mode (Real Mode), and Protected Virtual Ad- dress Mode (Protected Mode). In Real Mode the B0386 operates as a very fast 80B6, but with 32-bit extensions if desired. Real Mode is required primari-

Iy to setup the processor for Protected Mode opera- tion. Protected Mode provides access to the sophis- ticated memory management, paging and privilege capabilities of the processor.

Within Protected Mode, software can perform a task switch to enter into tasks designated as Virtual B086 Mode tasks. Each such task behaves with BOB6 se- mantics, thus allowing BOB6 software (an application program, or an entire operating system) to execute. The Virtual 80B6 tasks can be isolated and protect- ed from one another and the host B0386 operating system, by the use of paging, and the 110 Permis- sion Bitmap.

Finally, to facilitate high performance system hard- ware designs, the 80386 bus interface offers ad- dress pipelining, dynamic data bus sizing, and direct Byte Enable signals for each byte of the data bus. These hardware features are described fully begin- ning in Section 5.

2.2 REGISTER OVERVIEW

The B0386 has 32 register resources in the following categories:

oGeneral Purpose Registers

oSegment Registers

oInstruction Pointer and Flags

oControl Registers

oSystem Address Registers

oDebug Registers

oTest Registers.

The registers are a superset of the 8086, 80186 and B0286 registers, so all 16-bit 8086, B0186 and 802B6 registers are contained within the 32-bit 803B6.

Figure 2-1 shows all of B0386 base architecture reg- isters, which include the general address and data registers, the instruction pointer, and the flags regis- ter. The contents of these registers are task-specific, so these registers are automatically loaded with a new context upon a task switch operation.

The base architecture also includes six directly ac- cessible segments, each up to 4 Gbytes in size. The segments are indicated by the selector values placed in 80386 segment registers of Figure 2-1. Various selector values can be loaded as a program executes, if desired.

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