3.4 Protection
.................................................................
3-10
3.4.1
Privilege
................................................................
3-10
3.4.2 Privileged Instructions
....................................................
3-12
3.4.3 Segment Protection
......................................................
3-12
3.4.4 Page Protection
.........................................................
3-13
3.5 System Calls
...............................................................
3-13
3.6 Interrupts and Exceptions
....................................................
3-14
3.6.1
Interrupt Descriptor Table
.................................................
3-15
3.6.2 Debug Exceptions and Registers
...........................................
3-16
3.7
Input/Output
...............................................................
3-17
CHAPTER 4 ARCHITECTURAL COMPATIBILITY 4.1
80286 Compatibility
.........................................................
4-1
4.2
Real
and Virtual
86
Modes
....................................................
4-1
CHAPTER 5 HARDWARE IMPLEMENTATION 5.1
Internal Design
.............................................................
5-1
5.2 External Interface
...........................................................
5-3
5.2.1
Clock
..................................................................
5-3
5.2.2 Data and Address Buses
..................................................
5-3
5.2.3 Bus Cycle Definition
.....................................................
5-4
5.2.4 Bus Cycle Control
.......................................................
5-4
5.2.5 Dynamic Bus Sizing
......................................................
5-7
5.2.6 Processor Status and Control
..............................................
5-7
5.2.7 Coprocessor Control
.....................................................
5-7
BOOK II 80386 High Performance Microprocessor with Integrated Memory Management
..............
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iv