Intel 80386 manual Debug Eceptions and Registers

SYSTEM ARCHITECTURE

Ideally, interrupts should be handled by tasks, not procedures, because an interrupt is generally unrelated to the task it interrupts. Moreover, an interrupt handler should have its own resources (for example, its own stack) rather than "inherit- ing" those of whatever task happens to be running when the interrupt occurs. On the other hand, a task switch takes longer than a procedure call (17 VS. 3.6 microseconds) because the pro- cessor saves and restores its registers when it switches tasks. Systems that are extremely sen- sitive to interrupt latency can handle interrupts with procedures.

3.6.2Debug E){ceptions and Registers

Like most processors, the 80386 has a breakpoint instruction that can be used to invoke a debugger when it is executed. The 80386's principal de- bugging support, however, takes the form of the debug registers shown in Figure 3-11. The debug registers support both instruction breakpoints and data breakpoints. Data breakpoints are an important innovation that can save hours of debugging time by pinpointing, for example, exactly when a data structure is being overwritten.

31	o
BREAKPOINT ADDRESS 0	ORO
BREAKPOINT ADDRESS 1	DR1
BREAKPOINT ADDRESS 2	DR2
BREAKPOINT ADDRESS 3	DR3
(RESERVED BY INTEL)	DR4
(RESERVED BY INTEL)	DR5
DEBUG STATUS	DR6
DEBUG CONTROL	DR7

Figure 3-11. Debug Registers

The breakpoint registers also eliminate the contor- tions required to write a breakpoint instruction into code that is write-protected or shared by multiple tasks.

An 80386 debugger is implemented as the handler for exception number 1. The processor can be directed to invoke the debugger after every instruction (by setting TF, the Single Step Trap Flag), upon selected task switches, or upon occurrence of a breakpoint condition defined in one of the debug registers. By inspecting the Debug Status Register the debug exception handler can determine which of these caused it to be invoked. By having itself invoked on task switches, the debugger can reload the debug registers with values applicable to the new task.

The 80386 can monitor up to four breakpoint conditions simultaneously, invoking the debug exception handler whenever one of these condi- tions occurs. Each breakpoint condition is defined by the content of a debug register; these registers may be loaded and stored with privileged forms ofthe Move instruction. A breakpoint condition consists of a 32-bit linear address, a 2-bit length field, and an access field; the latter two items are specified in fields of DR7, the Debug Control Register. A breakpoint condition's address and length form an address range that the processor checks on each memory reference. The access field defines the type of access for which the processor is to raise exception 1. Three types of access may be specified:

1.Instruction at address executed.

2.Data written in address range.

3.Data read or written in address range.

3.7InpuVOutput

An 80386-based system can map I/O devices into the processor's memory space or into a separate I/O space. Memory-mapped I/O devices can be read or written using memory reference instructions such as Move, Or, and the like.

3-16