Intel 80386 manual Interrupt Signals

80386

5.2.8.4 COPROCESSOR ERROR (ERROR#)

This input signal indicates that the previous coproc- essor instruction generated a coprocessor error of a type not masked by the coprocessor'scontrol regis- ter. This input is automatically sampled by the 80386 when a coprocessor instruction is encountered, and if asserted, the 80386 generates exception 16 to ac- cess the error-handling software.

Several coprocessor instructions, generally those which clear the numeric error flags in the coproces- sor or save coprocessor state, do execute without the 80386 generating exception 16 even if ER- ROR # is asserted. These instructions are FNINIT, FNCLEX, FSTSW, FSTSWAX, FSTCW, FSTENV, FSAVE, FESTENV and FESAVE.

ERROR # is level-sensitive and is allowed to be asynchronous to the CLK2 signal.

ERROR# serves an additional function. If ERROR# is LOW no later than 20 CLK2 periods after the fail- ing edge of RESET and remains LOW at least until the 80386 begins its first bus cycle, an 80387 is as- sumed to be present (ET bit in CRO automatically gets set to 1). Otherwise, an 80287 (or no coproces- sor) is assumed to be present (ET bit in CRO auto- matically is reset to 0). See 5.5.3 Bus Activity Dur- ing and After Reset. Only the ET bit is set by this ERROR# pin test. Software must set the EM and MP bits in CRO as needed. Therefore, distinguishing 80287 presence from no coprocessor requires a software test and appropriately resetting or setting the EM bit of CRO (set EM = 1 when no coproces- sor is present). If ERROR# is sampled LOW after reset (indicating 80387) but software later sets EM = 1, the 80386 will behave as if no coprocessor is present.

5.2.9Interrupt Signals

5.2.9.1INTRODUCTION

The following descriptions cover inputs that can in- terrupt or suspend execution of the processor'scur- rent instruction stream.

5.2.9.2 MASKABLE INTERRUPT REQUEST (INTR)

When asserted, this input indicates a request for in- terrupt service, which can be masked by the 80386 Flag Register IF bit. When the 80386 responds to the INTR input, it performs two interrupt acknowl- edge bus cycles, and at the end of the second, latches an 8-bit interrupt vector on 00-07 to identify the source of the interrupt.

INTR is level-sensitive and is allowed to be asyn- chronous to the CLK2 signal. To assure recognition

of an INTR request, INTR should remain asserted until the first interrupt acknowledge bus cycle be- gins.

5.2.9.3NON-MASKABLE INTERRUPT REQUEST (NMI)

This input indicates a request for interrupt service, which cannot be masked by software. The non- maskable interrupt request is always processed ac- cording to the pointer or gate in slot 2 of the interrupt table. Because of the fixed NMI slot assignment, no interrupt acknowledge cycles are perfomed when processing NMI.

NMI is rising edge-sensitive and is allowed to be asynchronous to the CLK2 signal. To assure recog- nition of NMI, it must be negated for at least eight CLK2 periods, and then be asserted for at least eight CLK2 periods.

Once NMI processing has begun, no additional NMI'sare processed until after the next IRET in- struction, which is typically the end of the NMI serv- ice routine. If NMI is re-asserted prior to that time, however, one rising edge on NMI will be remem- bered for processing after executing the next. IRET instruction.

5.2.9.4 RESET (RESET)

This input signal suspends any operation in progress and places the 80386 in a known reset state. The 80386 is reset by asserting RESET for 15 or more CLK2 periods (80 or more CLK2 periods before re- questing self test). When RESET is asserted, all oth- er input pins are ignored, and all other bus pins are driven to an idle bus state as shown in Table 5-3. If RESET and HOLD are both asserted at a point in time, RESET takes priority even if the 80386 was in a Hold Acknowledge state prior to RESET asserted.

RESET is level-sensitive and must be synchronous to the CLK2 signal. If desired, the phase of the inter- nal processor clock, and the entire 80386 state can be completely synchronized to external circuitry by ensuring the RESET signal falling edge meets its ap- plicable setup and hold times, t25 and t26'

Table 5-3. Pin State (Bus Idle) During Reset

Pin Name	Signal Level During Reset
AOS#	High
00-031	High Impedance
BEO#-BE3#	Low
A2-A31	High
W/R#	Low
O/C#	High
M/IO#	Low
LOCK#	High
HLOA	Low

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