Encoding of Address Mode | Intel 80386 specs

80386

Register Specified by reg Field

During 32-Bit Data Operations

	reg	Function of w Field
	reg	(whenw = 0)	(whenw = 1)
		(whenw = 0)	(whenw = 1)
	000	AL	EAX
	001	CL	ECX
	010	DL	EDX
	011	BL	EBX
	100	AH	ESP
	101	CH	EBP
	110	DH	ESI
	111	BH	EDI

8.2.3.3ENCODING OF THE SEGMENT REGISTER (sreg) FIELD

The sreg field in certain instructions is a 2-bit field allowing one of the four 80286 segment registers to be specified. The sreg field in other instructions is a 3-bit field, allowing the 80386 FS and GS segment registers to be specified.

2-Bit sreg2 Field

	2-Bit	Segment
	2-Bit	Register
	sreg2 Field	Register
	sreg2 Field	Selected
		Selected
	00	ES
	01	CS
	10	SS
	11	DS

3-Bit sreg3 Field

	3-Bit	Segment
	3-Bit	Register
	sreg3 Field	Register
	sreg3 Field	Selected
		Selected
	000	ES
	001	CS
	010	SS
	011	DS
	100	FS
	101	GS
	110	do not use
	111	do not use

8.2.3.4 ENCODING OF ADDRESS MODE

Except for special instructions, such as PUSH or POP, where the addressing mode is pre-determined, the addressing mode for the current instruction is specified by addressing bytes following the primary opcode. The primary addressing byte is the "mod rim" byte, and a second byte of addressing informa- tion, the "s-i-b" (scale-index-base) byte, can be specified.

The s-i-b byte (scale-index-base byte) is specified when using 32-bit addressing mode and the "mod rim" byte has rim = 100 and mod = 00,01 or 10. When the sib byte is present, the 32-bit addressing mode is a function of the mod, ss, index, and base fields.

The primary addressing byte, the "mod rim" byte, also contains three bits (shown as TTT in Figure 8-1) sometimes used as an extension of the primary op- code. The three bits, however, may also be used as a register field (reg).

When calculating an effective address, either 16-bit addressing or 32-bit addressing is used. 16-bit ad· dressing uses 16-bit address components to calcu- late the effective address while 32-bit addressing uses 32-bit address components to calculate the ef- fective address. When 16-bit addressing is used, the "mod rim" byte is interpreted as a 16-bit addressing mode specifier. When 32-bit addressing is used, the "mod rim" byte is interpreted as a 32·bitaddressing mode specifier.

Tables on the following three pages define all en- codings of all 16-bit addressing modes and 32-bit addressing modes.

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Image 188

Intel 80386 manual Encoding of Address Mode

Contents

Page Inter Intel Corporation Table of Contents Chapter Architectural Compatibility Chapter Highlights Page 32-bit Architecture High-performance Implementation Highlights Extended Debugging Support Configurable ProtectionVirtual Memory Support Object Code Compatibility Summary Application Architecture Page Flags and Instruction Pointer RegistersGeneral Registers Numeric Coprocessor Registers Memory and logical Addressing Segment and Descriptor Registers Logical Address Translation Addressing Modes Data Types and Instructions Principal Data Types Stack Instructions Numeric Coprocessor Data TypesOther Instructions ~.,...I-------.-1 Byte String LII Miscellaneous Instructions Chapter System Architecture Page System Registers Multitasking Task Switching Task State Segment Addressing Address Translation Overview Segments Address Translation Overview Principal Descriptor Fields ~~~~~.II~~~ Pages Virtual Memory Linear to Physical Address Translation I I I Protection Privilege USing Privilege Levels Privileged Instructions Segment Protection Protection Interrupts and Exceptions 10. Gates as Protected Entry Points Interrupt Descriptor Table Debug Eceptions and Registers System Architecture Page Architectural Compatibility Page 80286 Compatibility Real and Virtual 86 Modes Architectural Compatibility Trapping Virtual 861\11ode System Calls Page Chapter Hardware Implementation Page Chapter Hardware Implementation Hardware Implementation Clock Data and Address Buses Bus Cycle Definition Bus Cycle Control Non-pipelined Bus Cycle Timing Bus Cycles with Pipelined Addresses Coprocessor Control Dynamic Bus SizingProcessor Status and Control Mixed 16- and 32-bit Accesses Chapter Data Sheet Page 80386 Update Notice Table of Contents Descriptor Tables Introduction Interrupt Descriptor TableSegment Descriptor Cache Privilege Validation Functional Data Package Thermal Specification 3.4Initiating and Maintaining Pipelined Address Pipelined Address with Dynamic Data Bus Sizing Base Architecture Introduction Register Overview Register Descriptions General Purpose RegistersInstruction Pointer Flags Register TSS Other Segment Physical Base Address Segment Limit Segment RegistersSegment Registers Descriptor Registers Loaded Automatically Segment Descriptor Registers Control RegistersFlects the current state of the ET bit MSW TS Task Switched, bit Fault Linear Address Register CR2System Address Registers Directory Base Register CR3 Compatibility Register AccessibilityDebug and Test Registers Instruction Set Overview IoplGdtr Idtr 2 80386 Instructions 2dLogical Instructions2a Data Transfer 2b Arithmetic Instructions 2e Bit Manipulation Instructions 2f. Program Control Instructions2g High Level Language Instructions 2h Protection Model 3 32-Bit Memory Addressing Modes Addressing Modes OverviewRegister and Immediate Modes Addressing Mode Calculations Differences Between 16 and 32 Bit Addresses Displacement Data TypesBase Register BX,BP Index Register SI,DI Scale Factor None LilliililillIl Sign ED rrrrrrrrl Address Spaces Memory OrganizationIntroduction I/O Space Segment Register Usage Interrupts Interrupts and Ecep~ionsInterrupt Processing Maskable Interrupt Non-Maskable Interrupt Software Interrupts Interrupt and Exception Priorities NMI 2.INTR Instruction Restart Reset and InitializationDouble Fault TLB Testing TestabilitySelf-Test Debugging Support Debug Registers Breakpoint InstructionSingle-Step Trap DR1 DR2DR3 DR4 Encoding Causing Breakpoint Usage Real Mode Architecture Real Mode Introduction Debug Status Register DR6 SET/RESET/COMPLEMENT Memory AddressingXchg ADD, OR, ADC, SBB Shutdown and Halt Reserved LocationsIntierrupts Protected Mode Addressing Addressing Mechanism Segmentation Introduction TerminologyDescriptor Tables Descriptor Tables Introduction Descriptors ByteAddress Segment Base 15 Segment Limit 15 Dptm typ , data gm,nt System Descriptor Formats Selector Offset 15Word Offset 31 Differences Between 386 and 286 Descriptors Segment Base 15Selector Fields Segment Descriptor Cache Nil R~L ~~~~~~~EL~~E~ ~A~~ ~I~I! ttl ~!~~~~E L~~E~~~s~ I~I! ~ J ~~?~~~~EL~~E~B~~E ~I~I~ tJ1 Privilege Levels Protection ConceptsRules of Privilege Privilege Level Transfers GOT/LOT CallRET,IRET CALL, JMP 80386 Task Switching Call Ga~es Initialization and Transition to Protected Mode Infef Tools for Building Protected PagingSystems Paging Concepts Paging Organization MechanismDescriptor Base Register Directory Level Protection R/W, U/S Bits Frame Address 31 ReservedTables DIRECTORY/TABLE Entries Translation Lookaside Buffer Paging Operation Paging In Virtual Mode Access TypeVirtual 8086 Environment Executing 8086 Programs Protection and 1/0 Permission Bitmap 24. Virtual 8086 Environment Memory Management Interrupt Handling Entering and Leaving Virtual Task Switches TO/FROM Virtual 8086 Mode ·25.Virtual 8086 Environment Interrupt and Call Handling For state saving i.e. push all registers in prolog, pop Introduction Clock CLK2 Data Bus do through Address Bus BEO# through BE3#, A2 through A31 Bus Cycle Definition Signals W/R#, D/C#, MIIO#, LOCK# Bus Control Signals Introduction Bus Arbitration Signals Coprocessor Interface Signals Interrupt Signals Signal Summary Memory and 1/0 Spaces BEO# Memory and 110 Organization Dynamic Data Bus Sizing Interfacing with 32- and 16-Bit Memories Cycles 1 and 1a Operand Alignment BEO# BHE# BLE# AD Li,\~~ P1 1.p2 .p1 1.p2 .p1 1.p2 .p1 1.p2 .p1 1.p2 .p1 1.p2 .p1 Address Pipelining ·9.Fastest Read Cycles with Pipelined Address Timing FOUR-BANK Interleaved Memory Address signal A2 selects bank Bit datapath to each bankTWO-BANK Interleaved Memory Read and Write Cycles Introduction NON-PIPELINED Address Xxxxx IxxxxXxxi Xxxix Ixxx 13 80386 Bus States not usIng pipelined address 3.3 NON·PIPELINED Address with Dynamic Data BUS Sizing ·14Asserting BS16# zero wait states, non·pipelinedaddress Xixxxxx Valid Xixxxx ,XXXXY~~~~ DOO¥ BSI6# XXX XXx XXX X .. IXXXXwOO~ J, XXX XXX1/ \ B516# ~~..tJ.~~~~~~~ BS16 # 44~~~...l-.lI...l Ready # 44~~.lI...l/l Bus Sizing with Pipelined Address Acknowledge ~ ,T1-T~-T2PJ ,T1PT2PJ Idle non-pipelined pipelinedPipelined IO#, D/c# Ffi 20 Complete Bus States including pipelined address Xxxxy ~j XDONTCAR~X~ x~ ~X~~lKX~ /..XXXX Xxxxx IXXXXIXXXXI.. /..DXXXIXXX ~ XxxxiyXxixxy ~ /..XIXXY ~ -XXIXXY Interrupt Acknowledge Inta Cycles ~--cp--- ----- ----- ----- ----- ~ Halt Indication Cycle 23.Halt Indication Cycle Shutdown Indication Cycle 24. Shutdown Indication Cycle Reset During Hold Acknowledge Bus Activity During and Following ResetOther Functional Descriptions Entering and Exiting Hold Acknowledge 26. Requesting Hold from Active Bus NA # negated SELF-TEST Signature Component and Revision Identifiers Component Revision Component Revision Stepping Identifier Name Software Testing for Coprocessor Presence CMD1 Mechanical Data Introduction PIN Assignment 000 0 0 0 000 0 0 Vee Vss Package Dimensions and Mounting 1654189~1 Package Thermal Specification Measure PGA Case Temperature Infef80386 Ill Power and Grounding Electrical Data D.C. Specifications Maximum Ratings 102 A.C. Specifications1 A.C. Spec Definitions Unit Min Max Operating Frequency MHz Half of CLK2 2 A.C. Specification Tables·4 -16 A.C. Characteristics Symbol Parameter 80386-16 80386-16 Min Unit Max 16 A.C. Characteristics Symbol ParameterSymbol Parameter Min 3 A.C. Test Loads 4 A.C. Timing Waveforms 80386 ~QW~OOg OOOIP@OOIMl~iiO@OO 106 MAX Itm PI~ Instruction SET 80386 Instruction Encoding 8o386Instructlon Set CIock Count Summary 111 ·1 Instruction Set Clock Count Summary 112 80386 Instructlon Set CIockCount S ummary Contlnued RIm ·1 80386 Instruction Set Clock Count Summary Doubleword Instruction Set Clock Count Summary 115 Instruction Set Clock Count Summarycontlnued BIT Manipulation Instruction Set Clock Count Summar +ml 7+ml 80386 Ins ruefIon SetCIoek CountSummary ConrInued Protected 119 120 80386 Instructlon Set CIockCountSummaay Contmued Interrupt Instructions O3861nstructlon Set CIockCount Summary Contlnued Bound Infef80386 80386 nstructlon Set CIockCount Summary Contlnued Ns ruetIon StCIe oekCount 5 ummary Contlnued Madear Overview ~~~\ 2 32-Bit Extensions of the Instruction Set Encoding of Instruction FieldsField Bits Encoding of Address Mode Osbx OSBX+d1611010 EOI OS EAX Scale Factor Encoding of Operation Direction NAENB/AE NE/NZ Domestic Sales Offices California United States