Intel 80386 manual Non-Maskable Interrupt, Software Interrupts

infef		80386
	Table 2-5. Interrupt Vector Assignments
		Instruction Which	Return Address
	Interrupt		Points to
Function		Can Cause		Type
	Number		Faulting
		Exception
			Instruction
Divide Error	0	DIV,IDIV	YES	FAULT
Debug Exception	1	any instruction	YES	TRAP'
NMllnterrupt	2	INT 2 orNMI	NO	NMI
One Byte Interrupt	3	INT	NO	TRAP
Interrupt on Overflow	4	INTO	NO	TRAP
Array Bounds Check	5	BOUND	YES	FAULT
Invalid OP-Code	6	Any Illegal Instruction	YES	FAULT
Device Not Available	7	ESC, WAIT	YES	FAULT
Double Fault	8	Any Instruction That Can		ABORT
		Generate an Exception
Invalid TSS	10	JMP, CALL, IRET, INT	YES	FAULT
Segment Not Present	11	Segment Register Instructions	YES	FAULT
Stack Fault	12	Stack References	YES	FAULT
General Protection Fault	13	Any Memory Reference	YES	FAULT
Page Fault	14	Any Memory Access or Code Fetch	YES	FAULT
Coprocessor Error	16	ESC, WAIT	YES	FAULT
Intel Reserved	17-32
Two Byte Interrupt	0-255	INTn	NO	TRAP

• Some debug exceptIOns may report both traps on the prevIOUS Instruclion, and faults on the next Instruction.

Note: Exception 9 no longer occurs on the 80386 due to the improved interface between the 80386 and its coprocessors.

tions, have an "interrupt window", between memory moves, which allows interrupts during long string moves). When an interrupt occurs the processor reads an 8-bit vector supplied by the hardware which identifies the source of the interrupt, (one of 224 user defined interrupts). The exact nature of the in- terrupt sequence is discussed in section 5.

The IF bit in the EFLAG registers is reset when an interrupt is being serviced. This effectively disables servicing additional interrupts during an interrupt service routine. However, the IF may be set explicitly by the interrupt handler, to allow the nesting of inter- rupts. When an IRET instruction is executed the original state of the IF is restored.

be to activate a power failure routine. When the NMI input is pulled high it causes an interrupt with an internally supplied vector value of 2. Unlike a normal hardware interrupt, no interrupt acknowledgment se- quence is performed for an NMI.

While executing the NMI servicing procedure, the 80386 will not service further NMI requests, until an interrupt return (IRET) instruction is executed or the processor is reset. If NMI occurs while currently servicing an NMI, its presence will be saved f9r serv- icing after executing the first IRET instruction. The IF bit is cleared at the beginning of an NMI interrupt to inhibit further INTR interrupts.

2.9.4 Non-Maskable Interrupt

Non-maskable interrupts provide a method of servic- ing very high priority interrupts. A common example of the use of a non-maskable interrupt (NMI) would

2.9.5 Software Interrupts

A third type of interruptiexception for the 80386 is the software interrupt. An INT n instruction causes

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