Intel 80386 manual Memory and 110 Organization, Dynamic Data Bus Sizing

intJ	80386
rrrrrrrrH ...---..,		~1%.
		~~
		W/
PHYSICAL		~
MEMORY	~ggggg~~~ I		------ - COPROCESSOR
4GBYTE	(NOTE 1)	W :+ (80387 OR 80287)
		V@
			/NOT / ),
		I	ACCESSIBLE.

~

OOOOrrrrH EJ}ACCESSIBLE

64 kBYTE PROGRAMMED

OOOOOOOOH 1..-__...1 OOOOOOOOH	I/O SPACE	231630-5
Physical Memory Space	1/0 Space

NOTE:

Since A31 is HIGH during automatic communication with coprocessor, A31 HIGH and M/IO# LOW can be used to easily generate a coprocessor select signal.

Figure 5-4. Physical Memory and I/O Spaces

5.3.3 Memory and 110 Organization

The 80386 datapath to memory and I/O spaces can be 32 bits wide or 16 bits wide. When 32-bits wide, memory and I/O spaces are organized naturally as arrays of physical 32-bit Owords. Each memory or I/O Oword has four individually addressable bytes at consecutive byte addresses. The lowest-addressed byte is associated with data signals 00-07; the highest-addressed byte with 024-031.

The 80386 includes a bus control input, B816#, that also allows direct connection to 16-bit memory or 110 spaces organized as a sequence of 16-bit words. Cycles to 32-bit and 16-bit memory or I/O devices may occur in any sequence, since the B816# control is sampled during each bus cycle. 8ee 5.3.4 DynamiC Data Bus Sizing. The Byte En- able signals, BEO # - BE3 #, allow byte granularity when addressing any memory or I/O structure, whether 32 or 16 bits wide.

5.3.4 Dynamic Data Bus Sizing

Dynamic data bus sizing is a feature allowing direct processor connection to 32-bit or 16-bit data buses for memory or I/O. A single processor may connect to both size buses. Transfers to or from 32- or 16-bit ports are supported by dynamically determining the bus width during each bus cycle. During each bus cycle an address decoding circuit or the slave de-

vice itself may assert B816 # for 16-bit ports, or ne- gate B816 # for 32-bit ports.

With B816 # asserted, the processor automatically converts operand transfers larger than 16 bits, or misaligned 16-bit transfers, into two or three trans- fers as required. All operand transfers physically oc- cur on 00-015 when B816# is asserted. There- fore, 16-bit memories or I/O devices only connect on data signals 00-015. No extra transceivers are required.

Asserting B816# only affects the processor when BE2# and/or BE3# are asserted during the current cycle. If only 00-015 are involved with the transfer, asserting B8 16 # has no affect since the transfer can proceed normally over a 16-bit bus whether B816# is asserted or not. In other words, asserting B816# has no effect when only the lower half of the bus is involved with the current cycle.

There are two types of situations where the proces- sor is affected by asserting B816#, depending on which Byte Enables are asserted during the current bus cycle:

Upper Half Only:

Only BE2# and/or BE3# asserted.

Upper and Lower Half:

At least BE1 #, BE2# asserted (and perhaps also BEO# and/or BE3#).

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