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Intel manual ·1 80386 Instruction Set Clock Count Summary, Doubleword

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Table 8·1 80386 Instruction Set Clock Count Summary (Continued)

INSTRUCTION	FORMAT
ARITHMETIC (Continued)
DIV ~ Divide (Unsigned)
Accumulator by Register/Memory	I11 11011 w Imod 11 0	r/ml
Divisor-Byte
-Word
-Doubleword
IDIV ~ Integer Divide (Signed)
Accumulator By Register/Memory	I1111011 w Imod 111	r/ml
Divisor-Byte
-Word
-Doubleword
AAD ~ ASCII Adjust for Divide	I 11010101 I 00001010 I
AAM ~ ASCII Adjust for Multiply	I11010100 I 00001010 I
CBW = Convert Byte to Word	I 100110001
CWO ~ Convert Word to Double Word I10011001 I
LOGIC
Shift Rotate Instructions
Not Through Carry (ROL, ROR, SAL, SAR, SHL, and SHR)
Register/Memory by 1	11101 OOOw ImOdTTT	r/ml
RegisterlMemory by CL	11101001 w Imod TIT	r/ml
Register/Memory by Immediate Count	I11 OOOOOw Imod TIT	r/mlimmed 8·bitdata
Through Carry (RCL and RCR)
Register/Memory by 1	I1101 OOOw ImOdTIT	r/ml
RegisterlMemory by CL	I1101001 w Imod TIT	r/ml

RegisterlMemory by Immediate Count 11 1 00000 w I mod TIT r/ml immed B·bitdata

TTTInstruction

000ROL

001ROR

010RCL

011RCR

100SHL/SAL

101SHR

111SAR

SHLD ~ Shift Left Double

Register/Memory by Immediate	I00001111	I1 01 001 00 Imod reg	r/mlimmed S-bit data
RegisterlMemory by CL	I 00001111	I 10100101 ImOdreg	r/ml
SHRD ~ Shift Right Double	I00001111
Register/Memory by Immediate	I00001111	I 10101100 ImOd reg	r/ml immed B·bitdata
RegisterlMemory by CL	I0000111 1 I 10101101 ImOd reg		r/ml
AND ~ And
Register to Register	I 001000 d w Imod reg r/ml

CLOCK COUNT

NOTES

RealReal

Address Protected Address Protected

Mode or Virtual Mode or Virtual Virtual Address Virtual Address

8086 Mode 8086 Mode

ModeMode

14/17	14/17	b,o	e,h
22/25	22/25	b,e	e,h
38/41	38/41	b,e	e,h
19/22	19/22	b,e	e,h
27/30	27/30	b,e	e,h
43/46	43/46	b,e	e,h

19 19

17 17

33

22

317 317b h

3/7 3/7b h

3/7 317b h

9/10 9/10 b h

9/10 9/10 b h

9/10 9/10 b h

3/7 3/7

317 3/7

3/7 317

3/7 317

22

114

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Intel manual ·1 80386 Instruction Set Clock Count Summary, Doubleword

Contents

Page Inter Intel Corporation Table of Contents Chapter Architectural Compatibility Chapter Highlights Page High-performance Implementation 32-bit ArchitectureHighlights Virtual Memory Support Configurable ProtectionExtended Debugging Support Summary Object Code CompatibilityApplication Architecture Page General Registers RegistersFlags and Instruction Pointer Numeric Coprocessor Registers Memory and logical Addressing Logical Address Translation Segment and Descriptor RegistersAddressing Modes Principal Data Types Data Types and InstructionsOther Instructions Numeric Coprocessor Data TypesStack Instructions ~.,...I-------.-1 Byte String LII Miscellaneous Instructions Chapter System Architecture Page Multitasking System RegistersTask State Segment Task SwitchingAddress Translation Overview AddressingAddress Translation Overview SegmentsPrincipal Descriptor Fields ~~~~~.II~~~ Pages Linear to Physical Address Translation Virtual MemoryI I I Privilege ProtectionUSing Privilege Levels Segment Protection Privileged InstructionsProtection 10. Gates as Protected Entry Points Interrupts and ExceptionsInterrupt Descriptor Table Debug Eceptions and Registers System Architecture Page Architectural Compatibility Page Real and Virtual 86 Modes 80286 CompatibilityArchitectural Compatibility Trapping Virtual 861\11ode System Calls Page Chapter Hardware Implementation Page Chapter Hardware Implementation Hardware Implementation Data and Address Buses ClockBus Cycle Control Bus Cycle DefinitionNon-pipelined Bus Cycle Timing Bus Cycles with Pipelined Addresses Processor Status and Control Dynamic Bus SizingCoprocessor Control Mixed 16- and 32-bit Accesses Chapter Data Sheet Page 80386 Update Notice Table of Contents Privilege Validation Descriptor Tables IntroductionInterrupt Descriptor Table Segment Descriptor CacheFunctional Data Pipelined Address with Dynamic Data Bus Sizing Package Thermal Specification3.4 Initiating and Maintaining Pipelined AddressRegister Overview Base Architecture IntroductionFlags Register Register DescriptionsGeneral Purpose Registers Instruction PointerTSS Segment Registers Descriptor Registers Loaded Automatically Segment RegistersOther Segment Physical Base Address Segment Limit MSW Segment Descriptor RegistersControl Registers Flects the current state of the ET bitDirectory Base Register CR3 TS Task Switched, bitFault Linear Address Register CR2 System Address RegistersDebug and Test Registers Register AccessibilityCompatibility Idtr Instruction Set OverviewIopl Gdtr2b Arithmetic Instructions 2 80386 Instructions2dLogical Instructions 2a Data Transfer2h Protection Model 2e Bit Manipulation Instructions2f. Program Control Instructions 2g High Level Language InstructionsRegister and Immediate Modes Addressing Modes Overview3 32-Bit Memory Addressing Modes Differences Between 16 and 32 Bit Addresses Addressing Mode CalculationsNone DisplacementData Types Base Register BX,BP Index Register SI,DI Scale FactorSign ED rrrrrrrrl LilliililillIlIntroduction Memory OrganizationAddress Spaces Segment Register Usage I/O SpaceMaskable Interrupt InterruptsInterrupts and Ecep~ions Interrupt ProcessingSoftware Interrupts Non-Maskable InterruptNMI 2.INTR Interrupt and Exception PrioritiesDouble Fault Reset and InitializationInstruction Restart Debugging Support TLB TestingTestability Self-TestSingle-Step Trap Breakpoint InstructionDebug Registers DR4 DR1DR2 DR3Usage Encoding Causing BreakpointDebug Status Register DR6 Real Mode Architecture Real Mode IntroductionADD, OR, ADC, SBB SET/RESET/COMPLEMENTMemory Addressing XchgIntierrupts Reserved LocationsShutdown and Halt Addressing Mechanism Protected Mode AddressingDescriptor Tables Introduction Segmentation IntroductionTerminology Descriptor TablesSegment Base 15 Segment Limit 15 DescriptorsByte AddressDptm typ , data gm,nt System Descriptor Formats Offset 31 SelectorOffset 15 WordSegment Descriptor Cache Differences Between 386 and 286 DescriptorsSegment Base 15 Selector FieldsNil R~L ~~~~~~~EL~~E~ ~A~~ ~I~I! ttl ~!~~~~E L~~E~~~s~ I~I! ~ J ~~?~~~~EL~~E~B~~E ~I~I~ tJ1 Rules of Privilege Protection ConceptsPrivilege Levels Privilege Level Transfers CALL, JMP GOT/LOTCall RET,IRET80386 Call Ga~es Task SwitchingInfef Initialization and Transition to Protected ModePaging Concepts Tools for Building ProtectedPaging SystemsDirectory Paging OrganizationMechanism Descriptor Base RegisterDIRECTORY/TABLE Entries Level Protection R/W, U/S BitsFrame Address 31 Reserved TablesPaging Operation Translation Lookaside BufferExecuting 8086 Programs Paging In Virtual ModeAccess Type Virtual 8086 Environment24. Virtual 8086 Environment Memory Management Protection and 1/0 Permission BitmapEntering and Leaving Virtual Interrupt HandlingTask Switches TO/FROM Virtual 8086 Mode For state saving i.e. push all registers in prolog, pop ·25.Virtual 8086 Environment Interrupt and Call HandlingClock CLK2 IntroductionAddress Bus BEO# through BE3#, A2 through A31 Data Bus do throughBus Cycle Definition Signals W/R#, D/C#, MIIO#, LOCK# Introduction Bus Control SignalsCoprocessor Interface Signals Bus Arbitration SignalsInterrupt Signals Signal Summary BEO# Memory and 1/0 SpacesDynamic Data Bus Sizing Memory and 110 OrganizationCycles 1 and 1a Interfacing with 32- and 16-Bit MemoriesBEO# BHE# BLE# AD Operand AlignmentLi,\~~ P1 1.p2 .p1 1.p2 .p1 1.p2 .p1 1.p2 .p1 1.p2 .p1 1.p2 .p1 ·9.Fastest Read Cycles with Pipelined Address Timing Address PipeliningTWO-BANK Interleaved Memory Address signal A2 selects bank Bit datapath to each bankFOUR-BANK Interleaved Memory Introduction Read and Write CyclesIxxx NON-PIPELINED AddressXxxxx Ixxxx Xxxi Xxxix13 80386 Bus States not usIng pipelined address ·14Asserting BS16# zero wait states, non·pipelinedaddress 3.3 NON·PIPELINED Address with Dynamic Data BUS SizingBSI6# XXX XXx XXX X .. IXXXXwOO~ J, XXX XXX1/ \ Xixxxxx ValidXixxxx ,XXXXY ~~~~ DOO¥B516# ~~..tJ.~~~~~~~ Bus Sizing with Pipelined Address BS16 # 44~~~...l-.lI...l Ready # 44~~.lI...l/lPipelined ~ ,T1-T~-T2PJ ,T1PT2PJ Idle non-pipelined pipelinedAcknowledge IO#, D/c# 20 Complete Bus States including pipelined address Ffi~ -XXIXXY Xxxxy ~j XDONTCAR~X~ x~ ~X~~lKX~ /..XXXXXxxxx IXXXXIXXXXI.. /..DXXXIXXX ~ Xxxxiy Xxixxy ~ /..XIXXY~--cp--- ----- ----- ----- ----- ~ Interrupt Acknowledge Inta Cycles23.Halt Indication Cycle Halt Indication Cycle24. Shutdown Indication Cycle Shutdown Indication CycleEntering and Exiting Hold Acknowledge Reset During Hold AcknowledgeBus Activity During and Following Reset Other Functional Descriptions26. Requesting Hold from Active Bus NA # negated Component and Revision Identifiers SELF-TEST SignatureComponent Revision Stepping Identifier Name Component RevisionCMD1 Software Testing for Coprocessor PresencePIN Assignment Mechanical Data Introduction000 0 0 0 000 0 0 Vee Vss 1654189~1 Package Dimensions and MountingMeasure PGA Case Temperature Package Thermal SpecificationIll Infef80386Electrical Data Power and GroundingMaximum Ratings D.C. Specifications1 A.C. Spec Definitions A.C. Specifications102 ·4 -16 A.C. Characteristics Symbol Parameter 80386-16 2 A.C. Specification TablesUnit Min Max Operating Frequency MHz Half of CLK2 Symbol Parameter Min 16 A.C. Characteristics Symbol Parameter80386-16 Min Unit Max 80386 ~QW~OOg OOOIP@OOIMl~iiO@OO 3 A.C. Test Loads 4 A.C. Timing Waveforms106 MAX Itm PI~ 80386 Instruction Encoding Instruction SET111 8o386Instructlon Set CIock Count Summary112 ·1 Instruction Set Clock Count SummaryRIm 80386 Instructlon Set CIockCount S ummary ContlnuedDoubleword ·1 80386 Instruction Set Clock Count Summary115 Instruction Set Clock Count SummaryBIT Manipulation Instruction Set Clock Count Summarycontlnued+ml 7+ml Instruction Set Clock Count SummarProtected 80386 Ins ruefIon SetCIoek CountSummary ConrInued119 120 Interrupt Instructions 80386 Instructlon Set CIockCountSummaay ContmuedBound O3861nstructlon Set CIockCount Summary Contlnued80386 nstructlon Set CIockCount Summary Contlnued Infef80386Madear Ns ruetIon StCIe oekCount 5 ummary Contlnued~~~\ OverviewBits 2 32-Bit Extensions of the Instruction SetEncoding of Instruction Fields FieldEncoding of Address Mode EOI OsbxOSBX+d16 11010OS EAX Scale Factor NE/NZ Encoding of Operation DirectionNAE NB/AECalifornia Domestic Sales OfficesUnited States