inter80386

4.3.4.10SEGMENT DESCRIPTOR REGISTER SETTINGS

The contents of the segment descriptor cache vary depending on the mode the 80386 is operating in. When operating in Real Address Mode, the segment base, limit, and other attributes within the segment cache registers are defined as shown in Figure 4-11 .

For compatiblity with the 8086 architecture, the base is set to sixteen times the current selector value, the limit is fixed at OOOOFFFFH, and the attributes are fixed so as to indicate the segment is present and fully usable. In Real Address Mode, the internal "privilege level" is always fixed to the highest level, level 0, so I/O and other privileged opcodes may be executed.

SEGMENT

 

DESCRIPTOR CACHE REGISTER CONTENTS

 

 

 

32 - BIT BASE

32 - BIT LIMIT

 

OTHER ATIRIBUTES

 

(UPDATED DURING SELECTOR

(FIXED)

 

(FIXED)

 

LOAD INTO SEGMENT REGISTER)

 

 

 

 

CONFORMING PRIVILEGE -----------------------

 

 

,

STACKSIZE ----------------------------

 

 

,

EXECUTABLE ------------------------

 

,

 

WRITEABLE -----------------------

 

,

 

R~DABLE-----------------------

 

,

 

EXPANSION DIRECTION

 

 

1

 

GRANULARITY

 

 

 

 

ACCESSED

 

 

 

1

 

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CS

16X

CURRENT CS SELECTOR"

OOOOFFFFH

Y 0

Y B U Y Y Y

- N

SS

16X

CURRENT SS SELECTOR

OOOOFFFFH

Y 0

Y B U Y Y N W -

DS

16X

CURRENT DS SELECTOR

OOOOFFFFH

Y 0

Y B U Y Y N

- -

ES

16X

CURRENT ES SELECTOR

OOOOFFFFH

Y 0

Y B U Y Y N

- -

FS

16X

CURRENT FS SELECTOR

OOOOFFFFH

Y 0

Y B U Y Y N

- -

GS

16X

CURRENT GS SELECTOR

OOOOFFFFH

Y 0

Y B U Y Y N

- -

231630-60

'Exceptthe 32-bit CS base is initialized to FFFFFOOOH after reset until first intersegment control transfer (e.g. intersegment CALL. or intersegment JMP, or INT). (See Figure 4-13 Example.)

Key: Y

= yes

D

= expand down

N

= no

B

= byte granularity

o

= privilege level 0

P

= page granularity

1

= privilege level 1

W

= push/pop 16-bit words

2

= privilege level 2

F

= push/pop 32·bitdwords

3

= privilege level 3

-

= does not apply to that segment cache register

U

= expand up

 

 

Figure 4-11. Segment Descriptor Caches for Real Address Mode

(Segment Limit and Attributes are Fixed)

42

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