Intel 80386 manual P1 1.p2 .p1 1.p2 .p1 1.p2 .p1 1.p2 .p1 1.p2 .p1 1.p2 .p1

inter80386

The definition of each bus cycle is given by three definition signals: M/IO#, W/R# and D/C#. At the same time, a valid address is present on the byte enable signals BEO # -BE3 # and other address sig- nals A2-A31. A status signal, ADS#, indicates when the 80386 issues a new bus cycle definition and address.

Collectively, the address bus, data bus and all asso- ciated control signals are referred to simply as "the bus".

When active, the bus performs one of the bus cycles below:

1)read from memory space

2)locked read from memory space

3)write to memory space

4)locked write to memory space

5)read from 1/0 space (or coprocessor)

Table 5-2 shows the encoding of the bus cycle defi- nition signals for each bus cycle. See section 5.2.5 Bus Cycle Definition.

The data bus has a dynamic sizing feature support- ing 32- and 16-bit bus size. Data bus size is indicated to the 80386 using its Bus Size 16 (BS16#) input. All bus functions can be performed with either data bus size.

When the 80386 bus is not performing one of the activities listed above, it is either Idle or in the Hold Acknowledge state, which may be detected by ex- ternal circuitry. The idle state can be identified by the 80386 giving no further assertions on its address strobe output (ADS#) since the beginning of its most recent bus cycle, and the most recent bus cy- cle has been terminated. The hold acknowledge state is identified by the 80386 asserting its hold ac- knowledge (HLDA) output.

6)write to 1/0 space (or coprocessor)

7)interrupt acknowledge

8)indicate halt, or indicate shutdown

The shortest time unit of bus activity is a bus state. A bus state is one processor clock period (two CLK2 periods) in duration. A complete data transfer occurs during a bus cycle, composed of two or more bus states.

	CYCLE 1		CYCLE 2		CYCLE 3
NON-PIPELINED NON-PIPELINED NON-PIPELINED
	(READ)		(READ)		(READ)
T1	T2	T1	T2	T1	T2

.p1 1.p2 .p1 1.p2 .p1 1.p2 .p1 1.p2 .p1 1.p2 .p1 1.p2 .p1

CLK2 [ (INPUT)

8EO#-8E3#, A2-A31, [ M/IO#, D/C#, WjR#

(OUTPUTS)

ADS# [

(OUTPUT)

NA# [

(INPUT)

READY# [ (INPUT)

LOCK# [ (OUTPUT)

00-031 [

(INPUT DURING READ)

231630-11

Fastest non·pipelinedbus cycles consist of T1 and T2

Figure 5·8.Fastest Read Cycles with Non·PipelinedAddress Timing

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