inter

 

 

80386

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

A TRANSFER REQUIRING TWO

 

 

 

 

 

 

CYCLES ON 16-81T DATA BUS

 

 

 

 

IDLE

 

CYCLE 1

 

 

CYCLE 1A

 

 

CYCLE 2

 

 

NON-PIPELINED

 

NON-PIPELINED

 

NON-PIPELINED

 

 

 

(READ ---- ! --- READ)

 

 

(WRITE)

 

 

 

PART ONE

 

 

PART TWO

 

 

 

 

Ti

T1

T2

T2

TI

T2

T2

T1

T2

T2

CLK2 [ -MnILM rmrtJl nILnILnILrtJlnIL

(82384 CLK) [ -VV V V V V V V V V

8EO #. 8El #

8E2 #. 8E3 #

A2- A31. M/IO#. D/C#

[ XIXXXXX VALID I

I

NEGATED DURING

i\

VALID 2

PART TWO

[ J.lXX.X) X

 

 

 

I

VALID I

 

 

VALID 2

 

 

 

W/R# [ ~~/

ADS#

[

LV

 

I

V

 

N TE: NA# MUST BE NEGATED"---

 

"---

 

 

 

 

 

 

 

HERE TO ALLOW RECOGNITION

 

 

 

 

 

OF ASSERTED BSI6# IN FINAL T2

 

 

NA#

[ XIXXXX ,XXXXY

'<X~~~~DOO()(¥

'X~~~~~{ XXXXrY

'( XXX

 

 

 

 

 

 

~

BUS ~ZE

BSI6# [ )[XXX :XX'x XXX X ).. "IXXXXwOO<~ J, XXX XXX'1/ '\

16-BIT

16-81T

BUS SIZE

BUS SIZE

READY # [ ) XXX)DOOC <XI ~ I IX) 'XY

~I IX 'XI ~

LOCK# [ )( Y.'J.'X'J~ .

DO- D15 [ - ---- ----

D16- D31 [ - --------

Key: On = physical data pin n dn = logical data bit n

VALID I

 

 

VALID 2

dO-dl5

---

d16-d31

dO-dl5

-----0--

--0<

 

 

 

OUT

IGNORED

 

IGNORED

d16-d31

--_.--0-- ---

--0

OUT

I

 

I

I

231630-19

Figure 5-15. Asserting 8S16# (one wait state, non-pipelined address)

generated for the two 16-bit bus cycles are closely related to each other. The addresses are the same except 8EO# and 8E1 # are always negated for the second cycle. This is because data on DO-D15 was already transferred during the first 16-bit cycle.

Figures 5-14 and 5-15 show cases where assertion of 8816# requires a second 16-bit cycle for com- plete operand transfer. Figure 5-14 illustrates cycles

without wait states. Figure 5-15 illustrates cycles with one wait state. In Figure 5-15 cycle 1, the bus cycle during which 8816# is asserted, note that NA# must be negated in the T2 state(s) prior to the last T2 state. This is to allow the recognition of 8816# asserted in the final T2 state. The relation of NA# and 8816# is given fully in 5.4.3.4 Pipelined Address, but Figure 5-15 illustrates this only pre- caution you need to know when using 8816# with non-pipelined address.

79

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Intel 80386 manual Xixxxxx Valid, Xixxxx ,XXXXY, ~~~~ Doo¥, BSI6# XXX XXx XXX X .. IXXXXwOO~ J, XXX XXX1