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intJ | 80386 |
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5. FUNCTIONAL DATA |
| At the appropriate time, acknowledgement is sig- | |||
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| nalled by asserting the 80386 READY # input. | |||
5.1 INTRODUCTION |
| The 80386 can relinquish control of its local buses | |||
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| to allow mastership by other devices, such as direct | |||
The 80386 features a straightforward functional in- | memory access channels. When relinquished, HLDA | ||||
terface to the external hardware. The 80386 has | is the only output pin driven by the 80386, providing | ||||
separate, parallel buses for data and address. The | |||||
data bus is | system. The | ||||
address bus outputs | ideal when driving the system from test equipment, | ||||
most directly usable form for the | and in | ||||
bus: 4 individual byte enable signals, and the 30 up- | Functional data covered in this chapter describes | ||||
dress buses are interpreted and controlled with their | the processor'shardware interface. First, the set of | ||||
associated control signals. |
| signals available at the processor pins is described | |||
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| (see 5.2 Signal Description). Following that are the | |||
A dynamic data bus sizing feature allows the proc- | signal waveforms occurring during bus cycles (see | ||||
essor to handle a mix of 32- and | 5.3 Bus Transfer Mechanism, 5.4 Bus Functional | ||||
es on a | Description and 5.5 Other Functional Descrip- | ||||
Sizing). If | tions). |
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tomatically makes any adjustment needed, even |
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performing another | 5.2 SIGNAL DESCRIPTION | ||||
transfer if that is necessary. | |||||
may be connected to |
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loss of performance. A new address pipelining op· | 5.2.1 | Introduction |
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tion is provided and applies to |
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es for substantially improved memory utilization, es- | Ahead is a brief description of the 80386 input and | ||||
pecially for the most heavily used memory resourc- | |||||
es. |
| output signals arranged by functional groups. Note | |||
| the # symbol at the end of a signal name indicates | ||||
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The address pipelining option, when selected, typ- | the active, or asserted, state occurs when the signal | ||||
is at a low Voltage. When no # is present after the | |||||
ically allows a given memory interface to operate | |||||
signal name, the signal is asserted when at the high | |||||
with one less wait state than would otherwise be | |||||
required (see 5.4.2 Address Pipelining). The pipe- | voltage level. |
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lined bus is also well suited to interleaved memory | Example signal: M/IO# - | High voltage indicates | |||
designs. For 16 MHz interleaved memory designs |
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| Memory selected | ||
with 100 ns access time DRAMs, zero wait states |
| - | Low voltage indicates | ||
can be achieved when pipelined addressing is se- |
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| 1/0 selected | |||
lected. When address pipelining is requested by the |
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external hardware, the 80386 will output the address | The signal descriptions sometimes refer to AC tim- | ||||
and bus cycle definition of the next bus cycle (if it is | |||||
ing parameters, such as "t25 Reset Setup Time" and | |||||
internally available) even while waiting for the cur- | |||||
"t26 Reset Hold Time." The values of these parame- | |||||
rent cycle to be acknowledged. |
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| ters can be found in Tables | ||||
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external cache designs, since the cache memory will | 5.2.2 | Clock (CLK2) |
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typically be fast enough to allow |
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cles. For maximum design flexibility, the address | CLK2 provides the fundamental timing for the | ||
pipelining option is selectable on a | |||
80386. It is divided by two internally to generate the | |||
basis. |
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| internal processor clock used for instruction execu- | ||
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The processor'sbus cycle | is the basic mechanism | tion. The internal clock is comprised of two phases, | |
"phase one" and "phase two." Each CLK2 period is |
for information transfer, either from system to proc- | a phase of the internal clock. Figure | |
essor, or from processor to system. 80386 bus cy- | ||
the relationship. If desired, the phase of the internal | ||
cles perform data transfer in a minimum of only two | ||
processor clock can be synchronized to a known | ||
clock periods. On a | ||
phase by ensuring the RESET signal falling edge | ||
80386 transfer bandwidth at 16 MHz is therefore 32 | ||
meets its applicable setup and hold times, t25 and | ||
Mbytes/sec. Any bus cycle will be extended for | ||
t26· | ||
more than two clock periods, however, if external | ||
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hardware withholds acknowledgement of the cycle. |
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