Intel 80386 manual Introduction, Clock CLK2

intJ	80386
5. FUNCTIONAL DATA		At the appropriate time, acknowledgement is sig-
		nalled by asserting the 80386 READY # input.
5.1 INTRODUCTION		The 80386 can relinquish control of its local buses
		to allow mastership by other devices, such as direct
The 80386 features a straightforward functional in-		memory access channels. When relinquished, HLDA
terface to the external hardware. The 80386 has		is the only output pin driven by the 80386, providing
separate, parallel buses for data and address. The		near-complete isolation of the processor from its
data bus is 32-bits in width, and bidirectional. The		system. The near-complete isolation characteristic is
address bus outputs 32-bit address values in the		ideal when driving the system from test equipment,
most directly usable form for the high-speed local		and in fault-tolerant applications.
bus: 4 individual byte enable signals, and the 30 up-		Functional data covered in this chapter describes
per-order bits as a binary value. The data and ad-
dress buses are interpreted and controlled with their		the processor'shardware interface. First, the set of
associated control signals.		signals available at the processor pins is described
		(see 5.2 Signal Description). Following that are the
A dynamic data bus sizing feature allows the proc-		signal waveforms occurring during bus cycles (see
essor to handle a mix of 32- and 16-bit external bus-		5.3 Bus Transfer Mechanism, 5.4 Bus Functional
es on a cycle-by-cycle basis (see 5.3.4 Data Bus		Description and 5.5 Other Functional Descrip-
Sizing). If 16-bit bus size is selected, the 80386 au-		tions).
tomatically makes any adjustment needed, even
performing another 16-bit bus cycle to complete the		5.2 SIGNAL DESCRIPTION
transfer if that is necessary. 8-bit peripheral devices
may be connected to 32-bit or 16-bit buses with no
loss of performance. A new address pipelining op·		5.2.1	Introduction
tion is provided and applies to 32-bit and 16-bit bus-
es for substantially improved memory utilization, es-		Ahead is a brief description of the 80386 input and
pecially for the most heavily used memory resourc-
es.		output signals arranged by functional groups. Note
		the # symbol at the end of a signal name indicates
The address pipelining option, when selected, typ-		the active, or asserted, state occurs when the signal
		is at a low Voltage. When no # is present after the
ically allows a given memory interface to operate
		signal name, the signal is asserted when at the high
with one less wait state than would otherwise be
required (see 5.4.2 Address Pipelining). The pipe-		voltage level.
lined bus is also well suited to interleaved memory		Example signal: M/IO# -		High voltage indicates
designs. For 16 MHz interleaved memory designs				Memory selected
with 100 ns access time DRAMs, zero wait states			-	Low voltage indicates
can be achieved when pipelined addressing is se-
				1/0 selected
lected. When address pipelining is requested by the
external hardware, the 80386 will output the address		The signal descriptions sometimes refer to AC tim-
and bus cycle definition of the next bus cycle (if it is
		ing parameters, such as "t25 Reset Setup Time" and
internally available) even while waiting for the cur-
		"t26 Reset Hold Time." The values of these parame-
rent cycle to be acknowledged.
		ters can be found in Tables 7-4 and 7-5.
Non-pipelined address timing, however, is ideal for
external cache designs, since the cache memory will		5.2.2	Clock (CLK2)
typically be fast enough to allow non-pipelined cy-

cles. For maximum design flexibility, the address		CLK2 provides the fundamental timing for the
pipelining option is selectable on a cycle-by-cycle
		80386. It is divided by two internally to generate the
basis.
		internal processor clock used for instruction execu-
The processor'sbus cycle	is the basic mechanism	tion. The internal clock is comprised of two phases,
		"phase one" and "phase two." Each CLK2 period is

for information transfer, either from system to proc-	a phase of the internal clock. Figure 5-2 illustrates
essor, or from processor to system. 80386 bus cy-
	the relationship. If desired, the phase of the internal
cles perform data transfer in a minimum of only two
	processor clock can be synchronized to a known
clock periods. On a 32-bit data bus, the maximum
	phase by ensuring the RESET signal falling edge
80386 transfer bandwidth at 16 MHz is therefore 32
	meets its applicable setup and hold times, t25 and
Mbytes/sec. Any bus cycle will be extended for
	t26·
more than two clock periods, however, if external
hardware withholds acknowledgement of the cycle.

60