Intel 80386 manual Bus Cycle Definition Signals W/R#, D/C#, MIIO#, LOCK#, High

80386

The Byte Enable outputs, BEO#-BE3#, directly in- dicate which bytes of the 32-bit data bus are in- volved with the current transfer. This is most conve- nient for external hardware.

BEO# applies to 00-07

BEl # applies to 08-015

BE2# applies to 016-023

BE3# applies to 024-031

The number of Byte Enables asserted indicates the physical size of the operand being transferred (1, 2, 3, or 4 bytes). Refer to section 5.3.6 Operand Align- ment.

When a memory write cycle or 1/0 write cycle is in progress, and the operand being transferred occu- pies only the upper 16 bits of the data bus (016- 031), duplicate data is simultaneously presented on the corresponding lower 16-bits of the data bus (00-D15). This duplication is performed for optimum write performance on 16-bit buses. The pattern of write data duplication is a function of the Byte En- ables asserted during the write cycle. Table 5-1 lists the write data present on 00-031, as a function of the asserted Byte Enable outputs BEO#-BE3#.

5.2.5Bus Cycle Definition Signals (W/R#, D/C#, MIIO#, LOCK#)

These three-state outputs define the type of bus cy- cle being performed. W/R # distinguishes between write and read cycles. D/C# distinguishes between data and control cycles. M/IO# distinguishes be- tween memory and 1/0 cycles. LOCK# distin- guishes between locked and unlocked bus cycles.

The primary bus cycle definition signals are W/R#, O/C# and M/IO#, since these are the signals driv- en valid as the ADS # (Address Status output) is driven asserted. The LOCK # is driven valid at the same time as the first locked bus cycle begins, which due to address pipelining, could be later than AOS# is driven asserted. See 5.4.3.4 Pipelined Ad- dress. The LOCK # is negated when the READY # input terminates the last bus cycle which was

locked..

Exact bus cycle definitions, as a function of W/R#, D/C#, and MI/IO#, are given in Table 5-2. Note one combination of W/R#, D/C# and M/IO# is never given when ADS# is asserted (however, that combination, which is listed as "does not occur," will occur during idle bus states when ADS# is not as- serted). If MIIO#, D/C#, and W/R# are qualified by ADS# asserted, then a decoding scheme may use the non-occurring combination to its best advan- tage.

		Table 5-1 Write Oata Ouplication as a Function of BEO#-BE3#
	80386 Byte Enables				80386 Write Oata			Automatic
BE3#	BE2#	BE1#	BEO# 024-031 016-023 08-015 00-07					Ouplication?
High	High	High	Low	undef	undef	undef	A	No
High	High	Low	High	undef	undef	B	undef	No
High	Low	High	High	undef	C	undef	C	Yes
Low	High	High	High	0	undef	0	undef	Yes
High	High	Low	Low	undef	undef	B	A	No
High	Low	Low	High	undef	C	B	undef	No
Low	Low	High	High	D	C	D	C	Yes
High	Low	Low	Low	undef	C	B	A	No
Low	Low	Low	High	D	C	B	undef	No
Low	Low	Low	Low	D	C	B	A	No

Key:

D= logical write data d24-d31 C = logical write data d16-d23 B = logical write data d8-d15 A = logical write data dO-d7

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