Intel 80386 manual Segment and Descriptor Registers, Logical Address Translation

APPLICATION ARCHITECTURE

logical address names a segment's descriptor. Conceptually, the processor determines a seg- ment's address by using the selector as an index into a descriptor table maintained by the operating system. Adding the offset part of the logical address to the base address obtained from the segment's descriptor produces the operand address.

2.2.3Segment and Descriptor Registers

To make logical addressing efficient, the 80386 provides six segment and descriptor registers (see Figure 2-5). In effect, these registers act as a programmer-controlled cache that eliminates selectors from most instructions and permits most logical addresses to be translated on-chip without consulting a descriptor table.

The address references of most programs cluster in a few small address ranges (this is the "locality ofreference"principle that makes virtual memory practical). For example, if a procedure is stored in a segment, many instructions are likely to be fetched from the segment before control passes

	LOGICAL ADDRESS
47	32 31
I SELECTOR	OFFSET
	l
	DESCRIPTOR TABLE

to another procedure in another segment. The 80386, under program control, exploits this locality of reference by keeping recently used selectors and descriptors in its on-chip registers. The on-chip descriptors enable the great majority of logical addresses to be translated without time-consuming memory references.

At any instant, up to six segments are addressable, the code segment, the stack segment, and up to four data segments. The CS, SS, DS, ES, FS, and GS segment registers contain the selectors for these segments. The corresponding descriptor registers contain the matching descriptors. If necessary, a program can make a new segment addressable by loading the new segment's selector into a segment register. The processor maintains the descriptor registers automatically, loading the proper descriptor whenever a program changes a segment register. (In fact, descriptor registers can only be loaded by the processor; they are inaccessible to programs.) Note that the Instruction Pointer contains the offset of the current instruction in the current code segment (defined by the CS register), and that register ESP contains the offset of the stack top in the

SEGMENT -

0

I

OPERAND

UP TO

232 BYTES

+

' ---DESCRIPTOR

-

Figure 2-4.Logical Address Translation

2-4