Intel 80386 I , nil , I

SEGMENT

80386

SELECTOR

4 3 2 1 a

I 0 I 0

----

a I a

11 11

nil

R~L

INDEX

~

TABLE

INDICATOR

TI-1

DESC~IPTOR

LOCAL

DESCRIPTOR

TABLE

DESCRIPTOR

NUMBER

TI-a!

NULL

GLOBAL

DESCRIPTOR

TABLE

Figure 4·10. El(smple Descriptor Selection

231630-59

Contents

Main Page i,~, TABLE OF CONTENTS BOOK I CHAPTER 1 HIGHLIGHTS CHAPTER 2 APPLICATION ARCHITECTURIE CHAPTER 3 SYSTEM ARCHITECTURE CHAPTER 4 ARCHITECTURAL COMPATIBILITY CHAPTER 5 HARDWARE IMPLEMENTATION BOOK II Page Page CHAPTER 1 HIGHLIGHTS 1.1 32-bit Architecture 1.2 High-performance Implementation 1-2 Ij 0 devices) can utilize the 80386's address 1.3 Virtual Memory Support 1.4 Configurable Protection 1.5 Extended Debugging Support 1.6 Object Code Compatibility 1-4 1.7 Summary Page Page CHAPTER 2 APPLICATION ARCHITECTURE 2.1 2.1.2 I 2.1.1 I I I 10PL I 2.2 2.2.1 logical Memory and Addressing l - APPLICATION ARCHITECTURE 2.2.4 Addressing Modes Figure 2-5. Segment and Descriptor Registers 2-5 2.3 Data Types and Instructions "I b 1-7 2.3.2 Numeric Coprocessor Data Types 2-7 2.3.3 Other Instructions 2.3.3.1 Stack Instructions 2.3.3.2 Control Transfer Instructions o 2-8 L -It -.l1 o I l' 2-9 ____ ---11 l 2.3.3.3 Miscellaneous Instructions 2-10 Page Page CHAPTER 3 SYSTEM ARCHITECTURE 3.1 3-1 System Registers I I 1 -- -- '" .. 3.3 Addressing 3.3.1 3-3 Address Translation Overview 3.3.2 Segments Translation 3-4 Address Figure 3-3. I 3-4 Descriptor Principal 3-4. ~t:~:: 3-6 [ .... I----------+- 3.3.3 Pages J n'-f 3-8 Address Physical to I page fault. In level 3.4 Protection 3.4.1 Privilege o. In 3-11 3.4.2 Privileged Instructions 3.4.3 Segment Protection 3-12 3.4.4 Page Protection 3.5 I I is t Points 3-14 Entry Protected 3.6.1. 3-15 4 16 14 3.6.2 1. I/O 1. is 0, I/O O. 3-17 Page Page Page CHAPTER 4 ARCHITECTURAL COMPATIBILITY is 4.1 80286 Compatibility 4-2 Page Page Page Page CHAPTER 5 HARDWARE IMPLEMENTATION - 5-1 5-1. Figure 5.1 K:====:> 5-2 5.2 External Interface 5.2.1 5-3 [ .. l\, v' C, DI WI 5.2.4 Bus Cycle Control 5-5 Figure 5-6 Pipelined with Cycles Bus 5.2.5 Dynamic Bus Sizing 5.2.6 Processor Status and Control 5-7 5.2.7 Coprocessor Control [ 9- Page Page HIGH PERFORMANCE 32-BIT MICROPROCESSOR ~NTEGRATED WITH MEMORY MANAGEMENT UPDATE NOTICE liD 2.8 1/0 Page 5. Page 2. BASE ARCHITECTURE 2.1 INTRODUCTION 2.2 REGISTER OVERVIEW I I I I I 2.3 2.3.1 2.3.2 8086 80386 O. 8086 80386 9 80386 2.3.4 Segment Registers - --- - - - 2.3.5 Segment Descriptor Registers f' 4. :;~~\I 2.3.6 Control Registers ~~---------------y--------------~} I = .0:1 80287/80387 = I I I " II 2.3.8 Debug and Test Registers I TEST CONTROL I 2.4 = INSTRUCTION = SET 2.4.1 GENERAL Table 2-2a Data Transfer ADDITION PURPOSE CONVERSION MULTIPLICATION infef 80386 2.5 ADDRESSING MODES 2.5.1 Addressing Modes Overview 2.5.2 Register and Immediate Modes 2.5.3 32-Bit Memory Addressing Modes 16 Between Differences 2.6 DATA TYPES infef rrrrrrrrl Figure 2-10. 80386 Supported Data AN~li~~E~~ ...... 2.7 MEMORY ORGANIZATION 2.7.1 Introduction 2.7.2 Address Spaces ...J ____ --+L 2.8 I/O SPACE 1/0 2.9 INTERRUPTS 2.9. i Interrupts and 2.9.2 Interrupt Processing 2.9.3 Maskable Interrupt infef 11 80386 17-32 0-255 2.9.6 Priorities 7. 9. 2.9.7 Instruction Restart A. 2.9.8 Double Fault 2.10 RESET AND INITIALIZATION 2.11 o c: TESTABILITY W#: W, [] Breakpoint 2.12.1 01 0 0 - I I I OG ~ RW Usage Encoding Causing Breakpoint Li as taken 3. i. REAL MODE ARCHITECTURE 3.1 REAL MODE INTRODUCTION ~J_----+_--'-j ~ 3.2 MEMORY ADDRESSING 4 3.3 RESERVED LOCATIONS 3.4 INTIERRUPTS PROTIECTIED 4. 3.5 SHUTDOWN AND HALT ! ~ ! ! ! ! ADDRESSING MECHANISM LlNEAR~ ~ 1 l SEGMENTATION 4.3.1 Segmentation Introduction 4.3.2 Terminology I 4.3.4 Descriptors o +4 typ' 37 7 "gm,nt data o. o o P 4.3.4.4 = 0 TYPE = C, GATE 4.3.4.6 9, lsi .. +4 I R~L nil 11 11 I ttl ~~~~~~~E _ ~I~I! ~A~~ ___ 12 J 1 ~:!~~~~E in __ -- - o Virtual 8086 Mode within Protected Mode (Segment Limit and Attributes are Fixed) 4.4 1/0 > of 4.4.2 Rules 80386 8086 11 80386 46 Page p-------------. , t : ---- I'~ H r- T + C 4.4.6 infef 4.4.7 Initialization and Transition to Protected Mode ITI """'" o ITI 1 ITI '1: ~ I 'r I 4.5.3 Page Level Protection (R/W, U/S Bits) 80386 4.5.4 Translation U = Lookaside Buffer 4.5.5 Paging Operation 4.5.6 Operating System Responsibilities 4.6 VIRTUAL 8086 ENVIRONMENT 4.6.1 Executing 8086 Programs 4.6.2 Virtual 8086 Mode Addressing Mechanism WI!! 4.6.4 Protection and o. Permission Bitmap 80386 a + Interrupt 4.6.5 [0' 4.6.6.2 Page 5. FUNCTIONAL DATA 5.1 5.2 INTRODUCTION SIGNAL DESCRIPTION 5.2.1 R~~~: through A2 Bus (BEO# Address MIIO#, LOCK#) 80386 Control 5.2.6 Bus Signals 5.2.7 Bus Arbitration Signals 5.2.8 Coprocessor Interface Signals 5.2.9 Interrupt Signals 80386 5.2.10 Signal Summary 5.3 BUS TRANSFER MECHANISM 5.3.1 Introduction -I -- (HI 5.3.2 ....... 1/0 and Memory W/ V@ ~ Organization 5.3.4 Dynamic Data Bus Sizing i intJ 80386 5.4 5.3.6 Operand Alignment BUS FUNCTIONAL DESCRIPTION 5.4.1 ---- = JllVi . Ib, Page 5.4.2 Address Pipelining Page 5.4.3 Read and Write Cycles 5.4.3.1 Bus Figure 5-11. Various ~~9' Cycles and Idle States with Non-Pipelined Address (zero wait states) / n 76 nn rut rut rut rut ----- -----~--< XXA Page -------<:t==~O~U~T~==t=) --0-- ---0--- I I nIL rm --0 --0-- -- ---- ~~..t::J.~~~~~~~ ~UI..~"!I'-~UI!oLlil~""'~,+;s.,,)I n np #' 44~~~...l'-.lI...l>( 44~~""''"''".lI...l/l-''''' c:_ ---- ,T1-T~-T2P'J ~ ..... W/R# [ of Figure 5-19. Details Address Pipelining During Cycles with Wait States " ~ . " " ffi rm V rm \f \f V V \f I rm.. 'I' '\\\ x.xxxr XJ\ I I I I 5.4.5 Halt Indication Cycle 5.4.6 Shutdown Indication Cycle the only signals distinguishing shutdown indication I /'V'I:'?~~~~ 00-031. 5.5 OTHER FUNCTIONAL DESCRIPTIONS 5.5.1 ACK~g~~EDGE~ Bus 5.5.3 ~~:.cJ( Page ..Qja~-4~~~~~~~~~~~~ 5.6 SELF-TEST SIGNATURE 5.7 COMPONENT AND REVISION IDENTIFIERS 80386 XXXXXXX> 92 RESET BUSY # should be held stable for B CLK2 periods before and after the CLK2 period in which NOTE inter 5.8 Software Testing 5.8.1 COPROCESSOR INTERFACING .... .... Pinout-View PGA Figure 6-1. 80386 VCC .... .... 10 10 11 11 12 .... .... .... .... .... .... .... o o Pin from Pinout-View Page 0;- + C Table 62. in 14 6.4 SPECIFICATION 98 infef ~ ~ Ii. I Characteristics o 7. ELECTRICAL DATA 7.1 VSS Vee Vss r- = SPECIFICATIONS ~--------------~A ____ intJ 7.5 A.C. SPECIFICATIONS 7.5.1 A.C. .... A.C. Spec Definitions intJ ~[Q)W~[RI]~~ = A.C. 7.5.2 3 9 M/IO#, W/R#, M/IO#, ~CL 7.5.4 A.C. Timing Waveforms [ [ Figure 74. Input Setup and Hold Timing Figure 75. Output Valid Delay Timing 'J @ 231630-43 Figure 76. Output Float Delay and HLDA Valid Delay Timing Figure 77. RESET Setup and Hold Timing, and Internal Phase D d Itm FOR 7.6 DESIGNING ! PL o 231630-76 Figure 7-9. ICE-3S6 Optional Interface Module Clearance Requirements (inches) AND INSTRUCTION SET COUNT CLOCK 8.1 I 111 <;; * 8 I 6'/26" I r/ml From Register 3/6 I 2/6 2/6 I immediate ! 2/7 immediate I L 4 4 I I 9-14/12-17 r/ml Table 81 80386 I ImOd reg ImOd r/ml I immed Bbit data ImOdreg reg Register to Register I I 6 6 I I I I 2/5 2 2 I 6 6 I rim/ 2/6 2/6 8086 I c 10PL s; to I I I 7+ml r/ml I 118 3 I I I rim I I full I I I 8-bitdispl I I 8-bitdispl I I I I I I I I I Full I I I I I I Table 8-1. 80386 I I I I Set Clock Count Summary (Continued) 7+mor3 Displacement , 80386 a e - (C Privilege Different I type I 37 b I I r/ml Range I 122 reg eee eeereg I eeereg infef 8 123 I N/A infef StCI 124 rIm! rIm :z Overview o)~~~\ rim rim 8.2.2 32-Bit Extensions of 8.2.3 Encoding 86/186/286 the Instruction Set = rim" rim" byte has rim = 100 and mod = 00,01 or 10. infef ,. Page xB 0 DOMESTIC SALES OFFICES CANADA