Vee Vss | Intel 80386 specification

intJ80386

		Table 6-1. 80386 PGA Pinout-Functional Grouping
Pin /Signal		Pin/ Signal		Pin/Signal		Pin/Signal
N2	A31	M5	031	A1	Vee	A2	Vss
P1	A30	P3	030	A5	Vee	A6	Vss
M2	A29	P4	029	A7	Vee	A9	Vss
L3	A28	M6	028	A10	Vee	81	Vss
N1	A27	N5	027	A14	Vee	85	Vss
M1	A26	P5	026	C5	Vee	811	Vss
K3	A25	N6	025	C12	Vee	814	Vss
L2	A24	P7	024	012	Vee	C11	Vss
L1	A23	N8	023	G2	Vee	F2	Vss
K2	A22	P9	022	G3	Vee	F3	Vss
K1	A21	N9	021	G12	Vee	F14	Vss
J1	A20	M9	020	G14	Vee	J2	Vss
H3	A19	P10	019	L12	Vee	J3	Vss
H2	A18	P11	018	M3	Vee	J12	Vss
H1	A17	N10	017	M7	Vee	J13	Vss
G1	A16	N11	016	M13	Vee	M4	Vss
F1	A15	M11	015	N4	Vee	M8	Vss
E1	A14	P12	014	N7	Vee	M10 Vss
E2	A13	P13	013	P2	Vee	N3	Vss
E3	A12	N12	012	P8	Vee	P6	Vss
01	A11	N13	011			P14	Vss
02	A10	M12	010	F12	CLK2		N.C.
03	A9	N14	09	F12	CLK2	A4	N.C.
C1	A8	L13	08			84	N.C.
C2	A7	K12	07	E14	AOS#	86	N.C.
C3	A6	L14	06			812	N.C.
B2	A5	K13	05	B10	W/R#	C6	N.C.
B3	A4	K14	04	A11	O/C#	C7	N.C.
A3	A3	J14	03	A12	MIIO#	E13	N.C.
C4	A2	H14	02	C10	LOCK#	F13	N.C.
A13	BE3#	H13	01		NA#		PEREQ
B13	BE2#	H12	DO	013	NA#	C8	PEREQ
C13	8E1#			C14	BS16#	B9	BUSY#
E12	BEO#			G13 REAOY#		A8	ERROR#
		014	HOLD	B7	INTR	B8	NMI
C9	RESET	M14	HLOA	B7	INTR	B8	NMI

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Intel 80386 manual Vee Vss

Contents

Page Inter Intel Corporation Table of Contents Chapter Architectural Compatibility Chapter Highlights Page High-performance Implementation 32-bit Architecture Highlights Virtual Memory Support Configurable ProtectionExtended Debugging Support Summary Object Code Compatibility Application Architecture Page General Registers RegistersFlags and Instruction Pointer Numeric Coprocessor Registers Memory and logical Addressing Logical Address Translation Segment and Descriptor Registers Addressing Modes Principal Data Types Data Types and Instructions Other Instructions Numeric Coprocessor Data TypesStack Instructions ~.,...I-------.-1 Byte String LII Miscellaneous Instructions Chapter System Architecture Page Multitasking System Registers Task State Segment Task Switching Address Translation Overview Addressing Address Translation Overview Segments Principal Descriptor Fields ~~~~~.II~~~ Pages Linear to Physical Address Translation Virtual Memory I I I Privilege Protection USing Privilege Levels Segment Protection Privileged Instructions Protection 10. Gates as Protected Entry Points Interrupts and Exceptions Interrupt Descriptor Table Debug Eceptions and Registers System Architecture Page Architectural Compatibility Page Real and Virtual 86 Modes 80286 Compatibility Architectural Compatibility Trapping Virtual 861\11ode System Calls Page Chapter Hardware Implementation Page Chapter Hardware Implementation Hardware Implementation Data and Address Buses Clock Bus Cycle Control Bus Cycle Definition Non-pipelined Bus Cycle Timing Bus Cycles with Pipelined Addresses Processor Status and Control Dynamic Bus SizingCoprocessor Control Mixed 16- and 32-bit Accesses Chapter Data Sheet Page 80386 Update Notice Table of Contents Interrupt Descriptor Table Descriptor Tables IntroductionSegment Descriptor Cache Privilege Validation Functional Data 3.4 Package Thermal SpecificationInitiating and Maintaining Pipelined Address Pipelined Address with Dynamic Data Bus Sizing Register Overview Base Architecture Introduction General Purpose Registers Register DescriptionsInstruction Pointer Flags Register TSS Segment Registers Descriptor Registers Loaded Automatically Segment RegistersOther Segment Physical Base Address Segment Limit Control Registers Segment Descriptor RegistersFlects the current state of the ET bit MSW Fault Linear Address Register CR2 TS Task Switched, bitSystem Address Registers Directory Base Register CR3 Debug and Test Registers Register AccessibilityCompatibility Iopl Instruction Set OverviewGdtr Idtr 2dLogical Instructions 2 80386 Instructions2a Data Transfer 2b Arithmetic Instructions 2f. Program Control Instructions 2e Bit Manipulation Instructions2g High Level Language Instructions 2h Protection Model Register and Immediate Modes Addressing Modes Overview3 32-Bit Memory Addressing Modes Differences Between 16 and 32 Bit Addresses Addressing Mode Calculations Data Types DisplacementBase Register BX,BP Index Register SI,DI Scale Factor None Sign ED rrrrrrrrl LilliililillIl Introduction Memory OrganizationAddress Spaces Segment Register Usage I/O Space Interrupts and Ecep~ions InterruptsInterrupt Processing Maskable Interrupt Software Interrupts Non-Maskable Interrupt NMI 2.INTR Interrupt and Exception Priorities Double Fault Reset and InitializationInstruction Restart Testability TLB TestingSelf-Test Debugging Support Single-Step Trap Breakpoint InstructionDebug Registers DR2 DR1DR3 DR4 Usage Encoding Causing Breakpoint Debug Status Register DR6 Real Mode Architecture Real Mode Introduction Memory Addressing SET/RESET/COMPLEMENTXchg ADD, OR, ADC, SBB Intierrupts Reserved LocationsShutdown and Halt Addressing Mechanism Protected Mode Addressing Terminology Segmentation IntroductionDescriptor Tables Descriptor Tables Introduction Byte DescriptorsAddress Segment Base 15 Segment Limit 15 Dptm typ , data gm,nt System Descriptor Formats Offset 15 SelectorWord Offset 31 Segment Base 15 Differences Between 386 and 286 DescriptorsSelector Fields Segment Descriptor Cache Nil R~L ~~~~~~~EL~~E~ ~A~~ ~I~I! ttl ~!~~~~E L~~E~~~s~ I~I! ~ J ~~?~~~~EL~~E~B~~E ~I~I~ tJ1 Rules of Privilege Protection ConceptsPrivilege Levels Privilege Level Transfers Call GOT/LOTRET,IRET CALL, JMP 80386 Call Ga~es Task Switching Infef Initialization and Transition to Protected Mode Paging Tools for Building ProtectedSystems Paging Concepts Mechanism Paging OrganizationDescriptor Base Register Directory Frame Address 31 Reserved Level Protection R/W, U/S BitsTables DIRECTORY/TABLE Entries Paging Operation Translation Lookaside Buffer Access Type Paging In Virtual ModeVirtual 8086 Environment Executing 8086 Programs 24. Virtual 8086 Environment Memory Management Protection and 1/0 Permission Bitmap Entering and Leaving Virtual Interrupt Handling Task Switches TO/FROM Virtual 8086 Mode For state saving i.e. push all registers in prolog, pop ·25.Virtual 8086 Environment Interrupt and Call Handling Clock CLK2 Introduction Address Bus BEO# through BE3#, A2 through A31 Data Bus do through Bus Cycle Definition Signals W/R#, D/C#, MIIO#, LOCK# Introduction Bus Control Signals Coprocessor Interface Signals Bus Arbitration Signals Interrupt Signals Signal Summary BEO# Memory and 1/0 Spaces Dynamic Data Bus Sizing Memory and 110 Organization Cycles 1 and 1a Interfacing with 32- and 16-Bit Memories BEO# BHE# BLE# AD Operand Alignment Li,\~~ P1 1.p2 .p1 1.p2 .p1 1.p2 .p1 1.p2 .p1 1.p2 .p1 1.p2 .p1 ·9.Fastest Read Cycles with Pipelined Address Timing Address Pipelining TWO-BANK Interleaved Memory Address signal A2 selects bank Bit datapath to each bankFOUR-BANK Interleaved Memory Introduction Read and Write Cycles Xxxxx Ixxxx NON-PIPELINED AddressXxxi Xxxix Ixxx 13 80386 Bus States not usIng pipelined address ·14Asserting BS16# zero wait states, non·pipelinedaddress 3.3 NON·PIPELINED Address with Dynamic Data BUS Sizing Xixxxx ,XXXXY Xixxxxx Valid~~~~ DOO¥ BSI6# XXX XXx XXX X .. IXXXXwOO~ J, XXX XXX1/ \ B516# ~~..tJ.~~~~~~~ Bus Sizing with Pipelined Address BS16 # 44~~~...l-.lI...l Ready # 44~~.lI...l/l Pipelined ~ ,T1-T~-T2PJ ,T1PT2PJ Idle non-pipelined pipelinedAcknowledge IO#, D/c# 20 Complete Bus States including pipelined address Ffi Xxxxx IXXXXIXXXXI.. /..DXXXIXXX ~ Xxxxiy Xxxxy ~j XDONTCAR~X~ x~ ~X~~lKX~ /..XXXXXxixxy ~ /..XIXXY ~ -XXIXXY ~--cp--- ----- ----- ----- ----- ~ Interrupt Acknowledge Inta Cycles 23.Halt Indication Cycle Halt Indication Cycle 24. Shutdown Indication Cycle Shutdown Indication Cycle Bus Activity During and Following Reset Reset During Hold AcknowledgeOther Functional Descriptions Entering and Exiting Hold Acknowledge 26. Requesting Hold from Active Bus NA # negated Component and Revision Identifiers SELF-TEST Signature Component Revision Stepping Identifier Name Component Revision CMD1 Software Testing for Coprocessor Presence PIN Assignment Mechanical Data Introduction 000 0 0 0 000 0 0 Vee Vss 1654189~1 Package Dimensions and Mounting Measure PGA Case Temperature Package Thermal Specification Ill Infef80386 Electrical Data Power and Grounding Maximum Ratings D.C. Specifications 1 A.C. Spec Definitions A.C. Specifications102 ·4 -16 A.C. Characteristics Symbol Parameter 80386-16 2 A.C. Specification TablesUnit Min Max Operating Frequency MHz Half of CLK2 Symbol Parameter Min 16 A.C. Characteristics Symbol Parameter80386-16 Min Unit Max 80386 ~QW~OOg OOOIP@OOIMl~iiO@OO 3 A.C. Test Loads 4 A.C. Timing Waveforms 106 MAX Itm PI~ 80386 Instruction Encoding Instruction SET 111 8o386Instructlon Set CIock Count Summary 112 ·1 Instruction Set Clock Count Summary RIm 80386 Instructlon Set CIockCount S ummary Contlnued Doubleword ·1 80386 Instruction Set Clock Count Summary 115 Instruction Set Clock Count Summary BIT Manipulation Instruction Set Clock Count Summarycontlnued +ml 7+ml Instruction Set Clock Count Summar Protected 80386 Ins ruefIon SetCIoek CountSummary ConrInued 119 120 Interrupt Instructions 80386 Instructlon Set CIockCountSummaay Contmued Bound O3861nstructlon Set CIockCount Summary Contlnued 80386 nstructlon Set CIockCount Summary Contlnued Infef80386 Madear Ns ruetIon StCIe oekCount 5 ummary Contlnued ~~~\ Overview Encoding of Instruction Fields 2 32-Bit Extensions of the Instruction SetField Bits Encoding of Address Mode OSBX+d16 Osbx11010 EOI OS EAX Scale Factor NAE Encoding of Operation DirectionNB/AE NE/NZ California Domestic Sales Offices United States