Intel 80386 BS16 # 44~~~...l-.lI...l Ready # 44~~.lI...l/l, Bus Sizing with Pipelined Address

intJ80386

IDLE		CYCLE 1
		NON-PIPELINED
		(WRITE)
Ti	n	T2	T2P

ClK2 [

(82384 ClK) [

BEO #- BD #' [

A2-A31,

M/IO#, D/C#

W/R # [ 44'..¥-l~.J(

ADS# [

BS16 # [ 44~~~...l'-.lI...l>(

READY # [ 44~~""''"''".lI...l/l-'''''

DO- D31 [

CYCLE 2		CYCLE 3			CYCLE 4		IDLE
PIPELINED		PIPELINED			PIPELINED
(READ)		(WRITE)			(READ)
np	T2P	n P	T2P	T1P	T21	T21	Ti

231630-21

Following any idle bus state (Ti) the address is always non-pipelined and NA# is only sampled during wait states. To start address pipelining after an idle state requires a non-pipelined cycle with at least one wait state (cycle 1 above).

The pipelined cycles (2, 3, 4 above) are shown with various numbers of wait states.

Figure 5-17. Fastest Transition to Pipelined Address Following Idle Bus State

2)The next address may appear as early as the bus state after NA# was sampled asserted (see Fig- ures 5-16 or 5-17). In that case, state T2P is en- tered immediately_ However, when there is not an internal bus request already pending, the next ad- dress will not be available immediately after NA# is asserted and T21 is entered instead of T2P (see Figure 5-19 Cycle 3)_ Provided the current bus cy- cle isn'tyet acknowledged by READY # asserted, T2P will be entered as soon as the 80386 does drive the next address. External hardware should therefore observe the AD8# output as confirma- tion the next address is actually being driven on the bus.

3)Once NA# is sampled asserted, the 80386 com- mits itself to the highest priority bus request that is pending internally_ It can no longer perform an- other 16-bit transfer to the same address should

8816# be asserted externally, so thereafter must assume the current bus size is 32 bits. Therefore if NA# is sampled asserted within a bus cycle, 8816# is ignored thereafter in that bus cycle (see Figures 5-16, 5-17, 5-19)_ Consequently, do not assert NA# during bus cycles which must have 8816# driven asserted. 8ee 5.4.3.6 Dynamic

Bus Sizing with Pipelined Address.

4)Any address which is validated by a pulse on the 80386 AD8# output will remain stable on the ad- dress pins for at least two processor clock peri- ods. The 80386 cannot produce a new address more frequently than every two processor clock periods (see Figures 5-16, 5-17, 5-19).

5)Only the address and bus cycle definition of the very next bus cycle is available. The pipelining ca- pability cannot look further than one bus cycle ahead (see Figure 5-19 Cycle 1).

81