Intel 80386 manual Addressing Modes

APPLICATION ARCHITECTURE

current stack segment (defined by the SS register).

To improve instruction encoding efficiency, most instructions do not name segment registers. Instead, the 80386 automatically selects a segment register based on the instruction being executed. For example, a Jump instruction implicitly refers to the CS register and a Push instruction uses the SS register. If necessary, a programmer can explicitly direct the 80386 to use a particular segment in an instruction by preceding the instruction with a one-byte segment override prefix. The prefix directs the processor to use a particular segment register to translate the address in the following instruction.

Note that a segment whose base address is 0 and whose limit is 4 gigabytes defines a 4-gigabyte logical address space. Because the processor selects segment registers automatically, an instruc- tion can name an operand anywhere in this 4- gigabyte space with a simple 32-bit offset. If, as illustrated in Figure 2-6, all the descriptor registers are loaded with base addresses of 0 and limits of 4 gigabytes, the segments effectively disappear. Every byte in the logical address space, whether

an instruction, a variable, or an item on the stack, is addressable with a simple 32-bit offset. Thus, the segment registers give the 80386 six instantancously addressable logical address spaces of up to 4 gigabytes each. When these segments coincide, a program sees a single 4- gigabyte logical address space identical to that provided by less-flexible 32-bit architectures.

2.2.4 Addressing Modes

The 80386 provides register and immediate addressing modes for operands that are located in registers or in instructions, respectively. More importantly, the 80386 provides the addressing modes needed to efficiently refer to elements in memory-based data structures such as arrays, records (structures), arrays of records, and records containing arrays. A program spccifies the offset part of a logical address using one of the 80386 memory addressing modes. The 80386 computes the offset part of a logical address by the following formula:

offset: = base + (index * scale) + displacement

15	SEGMENT	63	DESCRIPTOR
	SELECTOR		BASE ADDRESS. LIMIT ETC.·	CS (CODE)

55 (STACK)

os (DATA)

ES (DATA)

FS (DATAl

GS (DATA)

-ADDITIONAL DESCRIPTOR FIELDS ARE DESCRIBED IN CHAPTER 3.

Figure 2-5. Segment and Descriptor Registers

2-5