Intel 80386 manual Non-pipelined Bus Cycle Timing

HARDWARE IMPLEMENTATION

to provide two-clock access to high-speed cache and local memories of any size. (The effectiveness of a memory cache depends on its size relative to the reference patterns of the application.) The latter gives lower-speed memory systems more time to respond to a bus cycle while still keeping the 80386 running at maximum speed. External hardware can dynamically enable pipelining by asserting the NA (N ext Address) pin as described below. By presenting a dynamically selectable choice of bus cycle timings, the 80386 allows hardware engineers to use the mix of memory components that meets price, space, and per-

formance goals, and to adapt a design to exploit advances in memory technology.

Figure 5-5 shows the timing of a non-pipelined bus cycle. The 80386 outputs the bus cycle definition as described above and external hard- ware signals that it has responded to the bus cycle by asserting READY. If, as often is the case, another bus request is pending in the 80386 when READY is asserted, the processor outputs the next bus cycle definition. With pipelining disabled, the minimum time between address and data is two clocks. External hardware that

CYCLE 1	CYCLE 2	CYCLE 3
(READ)	(READ)	(READ)

CLK2 [ (INPUT)

ADDRESS AND [

DEFINITION (OUTPUTS)

ADS [

(OUTPUT)

NA [

(INPUT)

READY [ (INPUT)

DIl-D3l [

(INPUT FOR READ)

Figure 5-5. Non-pipelined Bus Cycle Timing

5-5