intJ
80386
quest,
and
is allowed to drive the next internally
pending address onto the
bus.
Asserting NA # there-
fore makes it impossible for the next bus cycle to
again
access the current address
on
A2-A31, such
as
may
be required when B8 16 # is asserted
by
the
external hardware.
been sampled asserted
in
the current cycle. If
NA#
is sampled asserted, the current data bus
size
is
assumed to be
32
bits.
2)
To
also avoid conflict, if
NA#
and
B816#
are
both asserted during the
same
sampling window,
B816#
asserted has priority
and
the 80386 acts
as
if
NA#
was negated at that time. Internal
80386 circuitry, shown conceptually
in
Figure
5-
18,
assures that
B816#
is sampled asserted and
NA#
is
sampled negated if both inputs are exter-
nally asserted at the same sampling window.
To avoid conflict, the 80386
is
designed with follow-
ing
two provisions:
1)
To avoid conflict, the 80386 is deSigned to ignore
B816#
in
the current
bus
cycle if
NA#
has already
CLK2[
(82384
CLK) [
BEO#,
BE1# [
BE2#, BE3#, [
A2, A31,
M/IO#,D/C#
W/R#[
ADS#[
READY#
[
LOCK# [
DO-D1S[
PREVIOUS
CYCLE
T2P
Jl.Jl

-V

TIP
ilJl
V
A
TRANSFER
REQUIRING
TWO
CYCLES
ON
16-BIT
BUS
PIPELINED
NON-PIPELINED
CYCLE
I~YCLE
lA
(WRITE
WRITE)
PART
ONE
PART
TWO
T2 T2
T1
T2
T2
ilJl
rtIl
rtIl
rtIl
rm
V
\f \f
V V
ALWAYS
CYCLE
2
NON-PIPELINED
(READ)
Tl
T2
T2P
rm
ilJl
rtIl
V V
\f :~
VALID
1 /NEGATED
DURING
rx
VALID
2 X
VALID
3
PART
TWO
I -X
VALID
1 X
VALID
2 X
VALID
3
-_/ \ -'---

-

/ '---V
\......../
'---{C
NOTE:
NA#
MUST
BE
NEGATED
IN
THESE
T'S
TO
ALLOW
RECOGNITION
OF
ASSERTED
BSI6#
IN
FINAL T2'5.
/XXXX'Y ~ (j '< X
DON'T
CAR~<X
~ '<x:~ ~X
~~)lK<X~
/.. 'X'X"X"X
32-81T
BUStSIZE
XXXXX IXXXX IXXXXI>.. /.. D<XXX IXXX)(>..
~
XXXXIY '(IXXXX
~
16-BIT
16-BIT
BUS
SIZE
BUS
SIZE
'5<500.--<XX IXXY ~ /..X)( IXXY ~ -<XX IXXY ~
VALID
1 X
VALID
2
dO-dIS dO-dIS
d16-d31
dO-dl
. ---@-{
OUT OUT
- ----
--<m
5
d16-d31
d16-d31
dl6-d
31
Dt6-D31
[ .
---~-{
OUT
}-------~
I I
Key:
On
~
physical data pin n
231630-25
dn
~
logical data bit n
Cycles 1 and 2 are pipelined. Cycle 1 a cannot be pipe lined, but its address can be inferred from that of Cycle
1,
to
externally sirnulate address
pipelining during Cycle 1
a.
Figure 5ยท21. Using
NA#
and
8516#
85