Intel 80386 manual Instruction Restart, Reset and Initialization, Double Fault

80386

2.9.7 Instruction Restart 2.10 RESET AND INITIALIZATION

The 80386 fully supports restarting all instructions after faults. If an exception is detected in the instruc- tion to be executed (exception categories 4 through 10 in Table 2-6c), the 80386 invokes the appropriate exception service routine. The 80386 is in a state that permits restart of the instruction, for all cases but those in Table 2-6c. Note that all such cases are easily avoided by proper design of the operating sys- tem.

Table 2-6c.Conditions Preventing

Instruction Restart

A. An instruction causes a task switch to a task whose Task State Segment is partially "not present". (An entirely "not present" TSS is re- startable.) Partially present TSS's can be avoided either by keeping the TSS'sof such tasks present in memory, or by aligning TSS segments to reside entirely within a single 4K page (for TSS segments of 4K bytes or less).

B. A coprocessor operand wraps around the top of a 64K-byte segment or a 4G-byte segment, and spans three pages, and the page holding the middle portion of the operand is "not pres- ent." This condition can be avoided by starting at a page boundary any segments containing coprocessor operands if the segments are ap- proximately 64K-200 bytes or larger (i.e. large enough for wraparound of the coprocessor operand to possibly occur).

Note that these conditions are avoided by using the operating system designs mentioned in this table.

When the processor is initialized or Reset the regis- ters have the values shown in Table 2-7. The 80386 will then start executing instructions near the top of physical memory, at location FFFFFFFOH. When the first InterSegment Jump or Call is executed, address lines A20-31 will drop low for CS-relative memory cycles, and the 80386 will only execute instructions in the lower one megabyte of physical memory. This allows the system designer to use a ROM at the top of physical memory to initialize the system and take care of Resets.

RESET forces the 80386 to terminate all execution and local bus activity. No instruction execution or bus activity will occur as long as Reset is active. Between 350 and 450 CLK2 periods after Reset be- comes inactive the 80386 will start executing in- structions at the top of physical memory.

Table 2·7.Register Values after Reset

Flag Word	UUUU0002H	Note 1
Machine Status Word (CRO) UUUUUUUOH Note 2
Instruction Pointer	OOOOFFFOH
Code Segment	FOOOH	Note 3
Data Segment	OOOOH
Stack Segment	OOOOH
Extra Segment (ES)	OOOOH
Extra Segment (FS)	OOOOH
Extra Segment (GS)	OOOOH
DX register	component and
	stepping ID	Note 5
All other registers	undefined	Note 4

2.9.8 Double Fault

A Double Fault (exception 8) results when the proc- essor attempts to invoke an exception service rou- tine for the segment exceptions (10, 11, 12 or 13), but in the process of doing so, detects an exception other than a Page Fault (exception 14).

One other cause of generating a Double Fault (ex- ception 8) is the 80386 detecting any other excep- tion when it is attempting to invoke the Page Fault (exception 14) service routine (for example, if a Page Fault is detected when the 80386 attempts to invoke the Page Fault service routine). Of course in any functional system, not only in 80386-based systems, the entire page fault service routine must remain "present" in memory.

When a Double Fault occurs, the 80386 invokes the exception service routine for exception 8.

NOTES:

1.EFLAG Register. The upper 14 bits of the EFLAGS reg- ister are undefined, VM (Bit 17) and RF (BIT) 16 are a as are all other defined flag bits.

2.CRO: (Machine Status Word). All of the defined fields in the CRO are a (PG Bit 31, TS Bit 3, EM Bit 2, MP Bit 1, and PE Bit 0) except for ET Bit 4 (processor ex1ension type). The ET Bit is set during Reset according to the type of Co- processor in the system. If the coprocessor is an 80387 then ET will be 1, if the coprocessor is an 80287 or no coprocessor is present then ET will be O. All other bits are undefined.

3.The Code Segment Register (CS) will have its Base Ad- dress set to FFFFOOOOH and Limit set to OFFFFH.

4.All undefined bits are Intel Reserved and should not be used.

5.OX register always holds component and stepping iden- tifier (see 5.7). EAX register holds self-test signature if self- test was requested (see 5.6).

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