Intel 80386 manual B516# ~~..tJ.~~~~~~~

80386

5.4.3.4PIPELINED ADDRESS

Address pipelining is the option of requesting the address and the bus cycle definition of the next, in- ternally pending bus cycle before the current bus cycle is acknowledged with READY # asserted. AD5# is asserted by the 80386 when the next ad- dress is issued. The address pipelining option is con- trolled on a cycle-by-cycle basis with the NA # input signal.

Once a bus cycle is in progress and the current ad- dress has been valid for at least one entire bus state, the NA# input is sampled at the end of every phase one until the bus cycle is acknowledged. Dur- ing non-pipelined bus cycles, therefore, NA# is sampled at the end of phase one in every T2. An example is Cycle 2 in Figure 5-16, during which NA # is sampled at the end of phase one of every T2 (it was asserted once during the first T2 and has no further effect during that bus cycle).

If NA # is sampled asserted, the 80386 is free to drive the address and bus cycle definition of the next bus cycle, and assert ADS #, as soon as it has a bus request internally pending. It may drive the next ad- dress as early as the next bus state, whether the current bus cycle is acknowledged at that time or not.

Regarding the details of address pipelining, the

80386 has the following characteristics:

1)For NA# to be sampled asserted, 8516# must be negated at that sampling window (see Figure 5-16 Cycles 3 and 4, and Figure 5-17 Cycles 2 through 4). If NA# and 8516# are both sampled asserted during the last T2 period of a bus cycle, 8516# asserted has priority. Therefore, if both are asserted, the current bus size is taken to be 16 bits and the next address is not pipelined. Con- ceptually, Figure 5-18 shows the internal 80386 logic providing these characteristics.

	IDLE	CYCLE 1			CYCLE 2		CYCLE 3		CYCLE 4		IDLE
		NON-PIPELINED			NON-PIPELINED		PIPELINED		PIPELINED
		(WRITE)			(READ)		(WRITE)		(READ)
	n	TI	T2	TI	T2	T2P	TIP	T2P	TI P	T21	n
CLK2	[
(82384 CLK)	[
BEO # - BE3 # [ ~""""V'-::-::7.:"'7'""--1\
A2-A31,				' ------)f---:---f'>-...,;;,,;::.:....~r)'~~~
MilO #. DIC #
W/R#	[

AD5# [

B516# [ ~~..t::J.~~~~~~~

READY # [ ~UI..~"!I'-~UI!oLlil~""'~,+;s.,,)I

00- 031 [

231630-20

Following any idle bus state (Ti). addresses are non·pipelined. Within non·pipelined bus cycles. NA" is only sampled during wait states. Therefore. to begin address pipelining during a group of non·pipelinedbus cycles requires a non'pipelinedcycle with at least one wait state (Cycle 2 above).

Figure 5-16. Transitioning to Pipelined Address During Burst of Bus Cycles

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