Intel 80386 manual Functional Data

4.PROTECTED MODE ARCHITECTURE (Continued)

4.6 Virtual 8086 Environment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 55

4.6.1 Executing 8086 Programs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 55 4.6.2 Virtual 8086 Mode Addressing Mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 55 4.6.3 Paging In Virtual Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 55 4.6.4 Protection and Virtual 8086 Mode to 1/0 Permission Bit Map. . . . . . . . . . . . . .. 56 4.6.5 Interrupt Handling. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 57 4.6.6 Entering and Leaving Virtual 8086 Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 57

4.6.6.1 Task Switches tolfrom Virtual 8086 Mode. . . . . . . . . . . . . . . . . . . . . . . . . .. 58 4.6.6.2 Transitions Through Trap and Interrupt Gates, and IRET . . . . . . . . . . . . .. 58

5. FUNCTIONAL DATA				60
5.1	Introduction			60
5.2	Signal Description			60
5.2.1		Introduction		60
5.2.2		Clock (CLK2)		60
5.2.3		Data Bus (DO through 031)		61
5.2.4		Address Bus (BEO# through BE3#, A2 through A31)		61
5.2.5		Bus Cycle Definition Signals (W/R#, D/C#, MilO, LOCK#)		62
5.2.6		Bus Control Signals		63
	5.2.6.1		Introduction	63
	5.2.6.2		Address Status (ADS #)	63
	5.2.6.3		Transfer Acknowledge (READY#)	63
	5.2.6.4		Next Address Request (NA #)	63
	5.2.6.5		Bus Size 16 (BS16#)	63
5.2.7		Bus Arbitration Signals		64
	5.2.7.1		Introduction	64
	5.2.7.2		Bus Hold Request (HOLD)	64
	5.2.7.3		Bus Hold Acknowledge (HLDA)	64
5.2.8		Coprocessor Interface Signals		64
	5.2.8.1		Introduction	64
	5.2.8.2		Coprocessor Request (PEREa)	64
	5.2.8.3		Coprocessor Busy (BUSY#)	64
	5.2.8.4		Coprocessor Error (ERROR#)	65
5.2.9		Interrupt Signals		65
	5.2.9.1		Introduction	65
	5.2.9.2		Maskable Interrupt Request (INTR)	65
	5.2.9.3		Non-Maskable Interrupt Request (NMI)	65
	5.2.9.4		Reset (RESET)	65
5.2.10		Signal Summary		66
5.3.	Bus Transfer Mechanism			66
5.3.1		Introduction		66
5.3.2		Memory and 1/0 Spaces		67
5.3.3		Memory and 1/0 Organization		68
5.3.4		Dynamic Data Bus Sizing		68
5.3.5		Interfacing with 32- and 16-bit Memories		69
5.3.6		Operand Alignment		70
5.4	Bus Functional Description			70
5.4.1		Introduction		70
5.4.2		Address Pipelining		73
5.4.3		Read and Write Cycles		75
	5.4.3.1		Introduction	75
	5.4.3.2		Non-pipelined Address	76
	5.4.3.3		Non-pipelined Address with Dynamic Data Bus Sizing	78

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