Intel 80386 manual Pages

SYSTEM ARCHITECTURE

and segment registers) from the new task's TSS on task switches.

Tasks may share a segment in three ways (see Figure 3-5):

1.A segment whose descriptor is in the GDT is shared by all tasks.

2.Tasks that share an LOT share the segments described in the LOT; this approach is appropriate for closely cooperating tasks.

3.Descriptors in different LOTs may point to the same segment; such descriptors are called aliases. Aliases allow the unit of intertask sharing to be an individual segment, rather than all segments in a descriptor table.

3.3.3Pages

Whether a task's logical address space consists of one segment or many, an operating system can subdivide the linear address space into pages. To an operating system, pages are convenient units for allocation and relocation because they are all the same size. Pages also provide a way to protect portions of large segments and, impor- tantly, provide a convenient unit for imple- menting virtual memory. These applications of paging are discussed in subsequent sections.

An 80386 page is 4K bytes long. This size is consistent with the industry trend toward larger pages and it helps performance in two ways. First, it provides a high page cache hit ratio given the cache size that can reasonably be implemented on-chip with current technology. (The 80386's on-chip page cache is described shortly). Second, 4K bytes is an efficient unit for disk transfer; most operating systems run- ning on machines with smaller page sizes must group pages into "clusters" to keep the number of disk transfers acceptably low.

An 80386 operating system enables paging by setting the PG (Paging Enabled) bit in Control Register 0 with a privileged instruction. When paging is enabled, the processor translates a

linear address to a physical address with the aid of page tables. Page tables are the counterparts of segment descriptor tables; as a task's segment descriptor table defines its logical address space, a task's page tables define its linear address space. Similar to superminis and mainframes, an 80386 task's page tables are arranged in a two-level hierarchy as shown in Figure 3-6. Each task can have its own page table directory. The 80386's CR3 (Page Table Directory Base) system register points to the running task's page table directory; the processor updates CR3 on each task switch, obtaining the new directory address from the new task's TSS. A page table directory is one page long and contains entries for up to 1,024 page tables. Page tables are also one page long, and the entries in a page table describe 1,024 pages. Thus, each page table maps 4 megabytes and a directory can map up to 4 gigabytes, the entire 32-bit physical address space.

Figure 3-6· shows in functional terms how the 80386 translates a linear address to a physical address when paging is enabled. The processor uses the upper 10 bits of the linear address as an index into the directory. The selected directory entry contains the address of a page table. The processor adds the middle 10 bits of the linear address to the page table address to index the page table entry that describes the target page. Adding the lower 12 bits of the linear address to the page address produces the 32-bit physical address.

To save the overhead of page ta ble lookups, the 80386 caches mapping information for the the 32 most recently used pages in an on-chiptranslation lookaside buffer (TLB). Only when it does not find the mapping information for a page in the TLB does the processor consult a memory-based directory or page table. As a rule, 98-99% of address references are TLB "hits," requiring no memory reference to translate. When a TLB "miss" does occur, the processor replaces an older TLB entry with the new entry; the locality

3-7