Intel 80386 manual Itm

inter80386

7.6 DESIGNING FOR ICE-386 USE

The 80386 in-circuit emulator product is ICE-386. Because of the high operating frequency of 80386 systems and ICE-386, there is no cable separating the ICE-386 probe module from the target system. The ICE-386 probe module has several electrical and mechanical characteristics that should be taken into consideration when designing the hardware.

Capacitive loading: ICE-386 adds up to 25 pF to each line.

Drive requirement: ICE-386 adds one standard TTL load on the CLK2 line, up to one advanced low- power Schottky TTL load per control signal line, and one advanced low-power Schottky TTL load per ad- dress, byte enable, and data line. These loads are within the probe module and are driven by the probe's80386, which has standard drive and load- ing capability listed in Tables 7-3 and 7-4.

Power requirement: For noise immunity the ICE- 386 probe is powered by the user system. The high- speed probe circuitry draws up to 0.7A plus the max- imum 80386 Icc from the user 80386 socket.

80386 location and orientation: The ICE-386 Proc- essor Module (PM), and the Optional Isolation Board (alB) used for extra electrical buffering of the

ICE initially, require clearance as illustrated in Fig- ures 7-8 and 7-9, respectively. Figures 7-8 and 7-9 also illustrate the via holes in these modules for rec- ommended orientation of a screw-actuated ZIF socket. Figure 7-10 illustrates the recommended ori- entation for a lever-actuated ZIF socket.

READY # drive: The ICE-386 system may be able to clear a user system READY# hang if the user's READY # driver is implemented with an open-collec- tor or tri-state device.

Optional Interface Board (OIB) and CLK2 speed reduction: When the ICE-386 processor probe is first attached to an unverified user system, the alB helps ICE-386 function in user systems with bus faults (shorted signals, etc.). After electrical verifica- tion it may be removed. Only when the alB is in- stalled, the user system must have a reduced CLK2 frequency of 16 MHz maximum.

Cache coherence: ICE-386 loads user memory by performing 80386 write cycles. Note that if the user system is not designed to update or invalidate its cache (if it has a cache) upon processor writes to memory, the cache could contain stale instruction code and/or data. For best use of ICE-386, the user should consider designing the cache (if any) to up- date itself automatically when processor writes oc- cur, or find another method of maintaining cache data coherence with main user memory.

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1.00 W/COVER			.98 WID COVER
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2 PL

231630-75

Figure 7-8. ICE-386 Processor Module Clearance Requirements (inches)

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