Signal Summary | Intel 80386 specification

80386

5.2.10 Signal Summary

	Table 5-4 summarizes the characteristics of all 80386 signals.
		Table 5-4_ 80386 Signal Summary
					Input	Output
			Active	Input!	Synch or	Output
	Signal Name	Signal Function	Active	Input!	Synch or	High Impedance
	Signal Name	Signal Function	State	Output	Asynch	High Impedance
			State	Output	Asynch	During HLDA?
					toCLK2	During HLDA?
					toCLK2
	CLK2	Clock	-	I	-	-
	00-031	Data Bus	High	1/0	S	Yes
	BEO#-BE3#	Byte Enables	Low	0	-	Yes
	A2-A31	Address Bus	High	0	-	Yes
	W/R#	Write-Read Indication	High	0	-	Yes
	OfC#	Data-Control Indication	High	0	-	Yes
	M/IO#	Memory-I/O Indication	High	0	-	Yes
	LOCK#	Bus Lock Indication	Low	0	-	Yes
	ADS#	Address Status	Low	a	-	Yes
	NA#	Next Address Request	Low	I	S	-
	BS16#	Bus Size 16	Low	I	S	-
	REAOY#	Transfer Acknowledge	Low	I	S	-
	HOLD	Bus Hold Request	High	I	S	-
	HLOA	Bus Hold Acknowledge	High	a	-	No
	PEREO	Coprocessor Request	High	I	A	-
	BUSY#	Coprocessor Busy	Low	I	A	-
	ERROR#	Coprocessor Error	Low	I	A	-
	INTR	Maskable Interrupt Request	High	I	A	-
	NMI	Non-Maskable Intrpt Request	High	I	A	-
	RESET	Reset	High	I	S	-

5.3BUS TRANSFER MECHANISM

5.3.1Introduction

All data transfers occur as a result of one or more bus cycles. Logical data operands of byte, word and double-word lengths may be transferred without re- strictions on physical address alignment. Any byte boundary may be used, although two or even three physical bus cycles are performed as required for unaligned operand transfers. See 5_3.4 Dynamic Data Bus Sizing and 5,3.6 Operand Alignment.

The 80386 address signals are designed to simplify external system hardware. Higher-order address bits are provided by A2-A31. Lower-order address in the form of BEO# -BE3# directly provides linear selects for the four bytes of the 32-bit data bus. Physical operand size information is thereby implicitly provid- ed each bus cycle in the most usable form.

Byte Enable outputs BEO#-BE3# are asserted when their associated data bus bytes are involved with the present bus cycle, as listed in Table 5-5. During a bus cycle, any possible pattern of contigu- ous, asserted Byte Enable outputs can occur, but never patterns having a negated Byte Enable sepa- rating two or three asserted Enables.

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Image 127

Intel 80386 manual Signal Summary

Contents

Page Inter Intel Corporation Table of Contents Chapter Architectural Compatibility Chapter Highlights Page High-performance Implementation 32-bit Architecture Highlights Virtual Memory Support Configurable ProtectionExtended Debugging Support Summary Object Code Compatibility Application Architecture Page General Registers RegistersFlags and Instruction Pointer Numeric Coprocessor Registers Memory and logical Addressing Logical Address Translation Segment and Descriptor Registers Addressing Modes Principal Data Types Data Types and Instructions Other Instructions Numeric Coprocessor Data TypesStack Instructions ~.,...I-------.-1 Byte String LII Miscellaneous Instructions Chapter System Architecture Page Multitasking System Registers Task State Segment Task Switching Address Translation Overview Addressing Address Translation Overview Segments Principal Descriptor Fields ~~~~~.II~~~ Pages Linear to Physical Address Translation Virtual Memory I I I Privilege Protection USing Privilege Levels Segment Protection Privileged Instructions Protection 10. Gates as Protected Entry Points Interrupts and Exceptions Interrupt Descriptor Table Debug Eceptions and Registers System Architecture Page Architectural Compatibility Page Real and Virtual 86 Modes 80286 Compatibility Architectural Compatibility Trapping Virtual 861\11ode System Calls Page Chapter Hardware Implementation Page Chapter Hardware Implementation Hardware Implementation Data and Address Buses Clock Bus Cycle Control Bus Cycle Definition Non-pipelined Bus Cycle Timing Bus Cycles with Pipelined Addresses Processor Status and Control Dynamic Bus SizingCoprocessor Control Mixed 16- and 32-bit Accesses Chapter Data Sheet Page 80386 Update Notice Table of Contents Privilege Validation Descriptor Tables IntroductionInterrupt Descriptor Table Segment Descriptor Cache Functional Data Pipelined Address with Dynamic Data Bus Sizing Package Thermal Specification3.4 Initiating and Maintaining Pipelined Address Register Overview Base Architecture Introduction Flags Register Register DescriptionsGeneral Purpose Registers Instruction Pointer TSS Segment Registers Descriptor Registers Loaded Automatically Segment RegistersOther Segment Physical Base Address Segment Limit MSW Segment Descriptor RegistersControl Registers Flects the current state of the ET bit Directory Base Register CR3 TS Task Switched, bitFault Linear Address Register CR2 System Address Registers Debug and Test Registers Register AccessibilityCompatibility Idtr Instruction Set OverviewIopl Gdtr 2b Arithmetic Instructions 2 80386 Instructions2dLogical Instructions 2a Data Transfer 2h Protection Model 2e Bit Manipulation Instructions2f. Program Control Instructions 2g High Level Language Instructions Register and Immediate Modes Addressing Modes Overview3 32-Bit Memory Addressing Modes Differences Between 16 and 32 Bit Addresses Addressing Mode Calculations None DisplacementData Types Base Register BX,BP Index Register SI,DI Scale Factor Sign ED rrrrrrrrl LilliililillIl Introduction Memory OrganizationAddress Spaces Segment Register Usage I/O Space Maskable Interrupt InterruptsInterrupts and Ecep~ions Interrupt Processing Software Interrupts Non-Maskable Interrupt NMI 2.INTR Interrupt and Exception Priorities Double Fault Reset and InitializationInstruction Restart Debugging Support TLB TestingTestability Self-Test Single-Step Trap Breakpoint InstructionDebug Registers DR4 DR1DR2 DR3 Usage Encoding Causing Breakpoint Debug Status Register DR6 Real Mode Architecture Real Mode Introduction ADD, OR, ADC, SBB SET/RESET/COMPLEMENTMemory Addressing Xchg Intierrupts Reserved LocationsShutdown and Halt Addressing Mechanism Protected Mode Addressing Descriptor Tables Introduction Segmentation IntroductionTerminology Descriptor Tables Segment Base 15 Segment Limit 15 DescriptorsByte Address Dptm typ , data gm,nt System Descriptor Formats Offset 31 SelectorOffset 15 Word Segment Descriptor Cache Differences Between 386 and 286 DescriptorsSegment Base 15 Selector Fields Nil R~L ~~~~~~~EL~~E~ ~A~~ ~I~I! ttl ~!~~~~E L~~E~~~s~ I~I! ~ J ~~?~~~~EL~~E~B~~E ~I~I~ tJ1 Rules of Privilege Protection ConceptsPrivilege Levels Privilege Level Transfers CALL, JMP GOT/LOTCall RET,IRET 80386 Call Ga~es Task Switching Infef Initialization and Transition to Protected Mode Paging Concepts Tools for Building ProtectedPaging Systems Directory Paging OrganizationMechanism Descriptor Base Register DIRECTORY/TABLE Entries Level Protection R/W, U/S BitsFrame Address 31 Reserved Tables Paging Operation Translation Lookaside Buffer Executing 8086 Programs Paging In Virtual ModeAccess Type Virtual 8086 Environment 24. Virtual 8086 Environment Memory Management Protection and 1/0 Permission Bitmap Entering and Leaving Virtual Interrupt Handling Task Switches TO/FROM Virtual 8086 Mode For state saving i.e. push all registers in prolog, pop ·25.Virtual 8086 Environment Interrupt and Call Handling Clock CLK2 Introduction Address Bus BEO# through BE3#, A2 through A31 Data Bus do through Bus Cycle Definition Signals W/R#, D/C#, MIIO#, LOCK# Introduction Bus Control Signals Coprocessor Interface Signals Bus Arbitration Signals Interrupt Signals Signal Summary BEO# Memory and 1/0 Spaces Dynamic Data Bus Sizing Memory and 110 Organization Cycles 1 and 1a Interfacing with 32- and 16-Bit Memories BEO# BHE# BLE# AD Operand Alignment Li,\~~ P1 1.p2 .p1 1.p2 .p1 1.p2 .p1 1.p2 .p1 1.p2 .p1 1.p2 .p1 ·9.Fastest Read Cycles with Pipelined Address Timing Address Pipelining TWO-BANK Interleaved Memory Address signal A2 selects bank Bit datapath to each bankFOUR-BANK Interleaved Memory Introduction Read and Write Cycles Ixxx NON-PIPELINED AddressXxxxx Ixxxx Xxxi Xxxix 13 80386 Bus States not usIng pipelined address ·14Asserting BS16# zero wait states, non·pipelinedaddress 3.3 NON·PIPELINED Address with Dynamic Data BUS Sizing BSI6# XXX XXx XXX X .. IXXXXwOO~ J, XXX XXX1/ \ Xixxxxx ValidXixxxx ,XXXXY ~~~~ DOO¥ B516# ~~..tJ.~~~~~~~ Bus Sizing with Pipelined Address BS16 # 44~~~...l-.lI...l Ready # 44~~.lI...l/l Pipelined ~ ,T1-T~-T2PJ ,T1PT2PJ Idle non-pipelined pipelinedAcknowledge IO#, D/c# 20 Complete Bus States including pipelined address Ffi ~ -XXIXXY Xxxxy ~j XDONTCAR~X~ x~ ~X~~lKX~ /..XXXXXxxxx IXXXXIXXXXI.. /..DXXXIXXX ~ Xxxxiy Xxixxy ~ /..XIXXY ~--cp--- ----- ----- ----- ----- ~ Interrupt Acknowledge Inta Cycles 23.Halt Indication Cycle Halt Indication Cycle 24. Shutdown Indication Cycle Shutdown Indication Cycle Entering and Exiting Hold Acknowledge Reset During Hold AcknowledgeBus Activity During and Following Reset Other Functional Descriptions 26. Requesting Hold from Active Bus NA # negated Component and Revision Identifiers SELF-TEST Signature Component Revision Stepping Identifier Name Component Revision CMD1 Software Testing for Coprocessor Presence PIN Assignment Mechanical Data Introduction 000 0 0 0 000 0 0 Vee Vss 1654189~1 Package Dimensions and Mounting Measure PGA Case Temperature Package Thermal Specification Ill Infef80386 Electrical Data Power and Grounding Maximum Ratings D.C. Specifications 1 A.C. Spec Definitions A.C. Specifications102 ·4 -16 A.C. Characteristics Symbol Parameter 80386-16 2 A.C. Specification TablesUnit Min Max Operating Frequency MHz Half of CLK2 Symbol Parameter Min 16 A.C. Characteristics Symbol Parameter80386-16 Min Unit Max 80386 ~QW~OOg OOOIP@OOIMl~iiO@OO 3 A.C. Test Loads 4 A.C. Timing Waveforms 106 MAX Itm PI~ 80386 Instruction Encoding Instruction SET 111 8o386Instructlon Set CIock Count Summary 112 ·1 Instruction Set Clock Count Summary RIm 80386 Instructlon Set CIockCount S ummary Contlnued Doubleword ·1 80386 Instruction Set Clock Count Summary 115 Instruction Set Clock Count Summary BIT Manipulation Instruction Set Clock Count Summarycontlnued +ml 7+ml Instruction Set Clock Count Summar Protected 80386 Ins ruefIon SetCIoek CountSummary ConrInued 119 120 Interrupt Instructions 80386 Instructlon Set CIockCountSummaay Contmued Bound O3861nstructlon Set CIockCount Summary Contlnued 80386 nstructlon Set CIockCount Summary Contlnued Infef80386 Madear Ns ruetIon StCIe oekCount 5 ummary Contlnued ~~~\ Overview Bits 2 32-Bit Extensions of the Instruction SetEncoding of Instruction Fields Field Encoding of Address Mode EOI OsbxOSBX+d16 11010 OS EAX Scale Factor NE/NZ Encoding of Operation DirectionNAE NB/AE California Domestic Sales Offices United States