80386

5.2.10 Signal Summary

Table 5-4 summarizes the characteristics of all 80386 signals.

 

 

 

 

Table 5-4_ 80386 Signal Summary

 

 

 

 

 

 

Input

Output

 

 

Active

Input!

Synch or

Signal Name

Signal Function

High Impedance

State

Output

Asynch

 

 

During HLDA?

 

 

 

 

toCLK2

 

 

 

 

 

CLK2

Clock

-

I

-

-

00-031

Data Bus

High

1/0

S

Yes

BEO#-BE3#

Byte Enables

Low

0

-

Yes

A2-A31

Address Bus

High

0

-

Yes

W/R#

Write-Read Indication

High

0

-

Yes

OfC#

Data-Control Indication

High

0

-

Yes

M/IO#

Memory-I/O Indication

High

0

-

Yes

LOCK#

Bus Lock Indication

Low

0

-

Yes

ADS#

Address Status

Low

a

-

Yes

NA#

Next Address Request

Low

I

S

-

BS16#

Bus Size 16

Low

I

S

-

REAOY#

Transfer Acknowledge

Low

I

S

-

HOLD

Bus Hold Request

High

I

S

-

HLOA

Bus Hold Acknowledge

High

a

-

No

PEREO

Coprocessor Request

High

I

A

-

BUSY#

Coprocessor Busy

Low

I

A

-

ERROR#

Coprocessor Error

Low

I

A

-

INTR

Maskable Interrupt Request

High

I

A

-

NMI

Non-Maskable Intrpt Request

High

I

A

-

RESET

Reset

High

I

S

-

5.3BUS TRANSFER MECHANISM

5.3.1Introduction

All data transfers occur as a result of one or more bus cycles. Logical data operands of byte, word and double-word lengths may be transferred without re- strictions on physical address alignment. Any byte boundary may be used, although two or even three physical bus cycles are performed as required for unaligned operand transfers. See 5_3.4 Dynamic Data Bus Sizing and 5,3.6 Operand Alignment.

The 80386 address signals are designed to simplify external system hardware. Higher-order address bits are provided by A2-A31. Lower-order address in the form of BEO# -BE3# directly provides linear selects for the four bytes of the 32-bit data bus. Physical operand size information is thereby implicitly provid- ed each bus cycle in the most usable form.

Byte Enable outputs BEO#-BE3# are asserted when their associated data bus bytes are involved with the present bus cycle, as listed in Table 5-5. During a bus cycle, any possible pattern of contigu- ous, asserted Byte Enable outputs can occur, but never patterns having a negated Byte Enable sepa- rating two or three asserted Enables.

66

Page 127
Image 127
Intel 80386 manual Signal Summary