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Intel manual 3 A.C. Test Loads 4 A.C. Timing Waveforms, 80386 ~QW~OOg OOOIP@OOIMl~iiO@OO

Models: 80386

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80386 ~[Q)W~OO©[g OOOIP@OOIMl~'iiO@OO

	Table 7-5. 80386-12 A.C. Characteristics (Continued)
Symbol	Parameter	80386-12	80386-12		Notes
Symbol	Parameter	Min	Max		Notes
		Min	Max
t15	NA# Setup Time	12
t16	NA# Hold Time	22
t17	8S16# Setup Time	14
t1B	8S16# Hold Time	22
t19	REAOY# Setup Time	22		7-4
t20	REAOY# Hold Time			7-4
t21	00-031 Read			7-4
	Setup Time
t22	00-031 Read			7-4
	Hold Time
t23	HOLO Setup Time		ns	7-4
t24	HOLO Hold Time		ns	7-4
t25	RESET Setup		ns	7-7
t26			ns	7-7
t27			ns	7-4	(Note 2)
t28			ns	7-4	(Note 2)
t29		18	ns	7-4	(Note 2)
t30		9	ns	7-4	(Note 2)

NOTES:

1.Float condition occurs when maximum output current becomes less than ILO in magnitude. Float delay is not 100% tested.

2.These inputs are allowed to be asynchronous to CLK2. The setup and hold specifications are given for testing purposes, to assure recognition within a specific CLK2 period.

7.5.3 A.C. Test Loads

7.5.4 A.C. Timing Waveforms

80386

OUTPUT~

~CL

231630-38

CL = 120 pF on A2-A31. 00-031

CL = 75 pF on BEO#-8E3#, W/R#, MIIO#, D/C#, ADS#,

LOCK#, HLDA

CL includes all parasitic capacitances.

Figure 7-2. A.C. Test Load

Figure 7-3. CLK2 Timing

105

Image 166

Intel manual 3 A.C. Test Loads 4 A.C. Timing Waveforms, 80386 ~QW~OOg OOOIP@OOIMl~iiO@OO

Contents

Page Inter Intel Corporation Table of Contents Chapter Architectural Compatibility Chapter Highlights Page 32-bit Architecture High-performance ImplementationHighlights Virtual Memory Support Configurable ProtectionExtended Debugging Support Object Code Compatibility SummaryApplication Architecture Page General Registers RegistersFlags and Instruction Pointer Numeric Coprocessor Registers Memory and logical Addressing Segment and Descriptor Registers Logical Address TranslationAddressing Modes Data Types and Instructions Principal Data TypesOther Instructions Numeric Coprocessor Data TypesStack Instructions ~.,...I-------.-1 Byte String LII Miscellaneous Instructions Chapter System Architecture Page System Registers MultitaskingTask Switching Task State SegmentAddressing Address Translation OverviewSegments Address Translation OverviewPrincipal Descriptor Fields ~~~~~.II~~~ Pages Virtual Memory Linear to Physical Address TranslationI I I Protection PrivilegeUSing Privilege Levels Privileged Instructions Segment ProtectionProtection Interrupts and Exceptions 10. Gates as Protected Entry PointsInterrupt Descriptor Table Debug Eceptions and Registers System Architecture Page Architectural Compatibility Page 80286 Compatibility Real and Virtual 86 ModesArchitectural Compatibility Trapping Virtual 861\11ode System Calls Page Chapter Hardware Implementation Page Chapter Hardware Implementation Hardware Implementation Clock Data and Address BusesBus Cycle Definition Bus Cycle ControlNon-pipelined Bus Cycle Timing Bus Cycles with Pipelined Addresses Processor Status and Control Dynamic Bus SizingCoprocessor Control Mixed 16- and 32-bit Accesses Chapter Data Sheet Page 80386 Update Notice Table of Contents Segment Descriptor Cache Descriptor Tables IntroductionInterrupt Descriptor Table Privilege ValidationFunctional Data Initiating and Maintaining Pipelined Address Package Thermal Specification3.4 Pipelined Address with Dynamic Data Bus SizingBase Architecture Introduction Register OverviewInstruction Pointer Register DescriptionsGeneral Purpose Registers Flags RegisterTSS Segment Registers Descriptor Registers Loaded Automatically Segment RegistersOther Segment Physical Base Address Segment Limit Flects the current state of the ET bit Segment Descriptor RegistersControl Registers MSWSystem Address Registers TS Task Switched, bitFault Linear Address Register CR2 Directory Base Register CR3Debug and Test Registers Register AccessibilityCompatibility Gdtr Instruction Set OverviewIopl Idtr2a Data Transfer 2 80386 Instructions2dLogical Instructions 2b Arithmetic Instructions2g High Level Language Instructions 2e Bit Manipulation Instructions2f. Program Control Instructions 2h Protection ModelRegister and Immediate Modes Addressing Modes Overview3 32-Bit Memory Addressing Modes Addressing Mode Calculations Differences Between 16 and 32 Bit AddressesBase Register BX,BP Index Register SI,DI Scale Factor DisplacementData Types NoneLilliililillIl Sign ED rrrrrrrrlIntroduction Memory OrganizationAddress Spaces I/O Space Segment Register UsageInterrupt Processing InterruptsInterrupts and Ecep~ions Maskable InterruptNon-Maskable Interrupt Software InterruptsInterrupt and Exception Priorities NMI 2.INTRDouble Fault Reset and InitializationInstruction Restart Self-Test TLB TestingTestability Debugging SupportSingle-Step Trap Breakpoint InstructionDebug Registers DR3 DR1DR2 DR4Encoding Causing Breakpoint UsageReal Mode Architecture Real Mode Introduction Debug Status Register DR6Xchg SET/RESET/COMPLEMENTMemory Addressing ADD, OR, ADC, SBBIntierrupts Reserved LocationsShutdown and Halt Protected Mode Addressing Addressing MechanismDescriptor Tables Segmentation IntroductionTerminology Descriptor Tables IntroductionAddress DescriptorsByte Segment Base 15 Segment Limit 15Dptm typ , data gm,nt System Descriptor Formats Word SelectorOffset 15 Offset 31Selector Fields Differences Between 386 and 286 DescriptorsSegment Base 15 Segment Descriptor CacheNil R~L ~~~~~~~EL~~E~ ~A~~ ~I~I! ttl ~!~~~~E L~~E~~~s~ I~I! ~ J ~~?~~~~EL~~E~B~~E ~I~I~ tJ1 Rules of Privilege Protection ConceptsPrivilege Levels Privilege Level Transfers RET,IRET GOT/LOTCall CALL, JMP80386 Task Switching Call Ga~esInitialization and Transition to Protected Mode InfefSystems Tools for Building ProtectedPaging Paging ConceptsDescriptor Base Register Paging OrganizationMechanism DirectoryTables Level Protection R/W, U/S BitsFrame Address 31 Reserved DIRECTORY/TABLE EntriesTranslation Lookaside Buffer Paging OperationVirtual 8086 Environment Paging In Virtual ModeAccess Type Executing 8086 ProgramsProtection and 1/0 Permission Bitmap 24. Virtual 8086 Environment Memory ManagementInterrupt Handling Entering and Leaving VirtualTask Switches TO/FROM Virtual 8086 Mode ·25.Virtual 8086 Environment Interrupt and Call Handling For state saving i.e. push all registers in prolog, popIntroduction Clock CLK2Data Bus do through Address Bus BEO# through BE3#, A2 through A31Bus Cycle Definition Signals W/R#, D/C#, MIIO#, LOCK# Bus Control Signals IntroductionBus Arbitration Signals Coprocessor Interface SignalsInterrupt Signals Signal Summary Memory and 1/0 Spaces BEO#Memory and 110 Organization Dynamic Data Bus SizingInterfacing with 32- and 16-Bit Memories Cycles 1 and 1aOperand Alignment BEO# BHE# BLE# ADLi,\~~ P1 1.p2 .p1 1.p2 .p1 1.p2 .p1 1.p2 .p1 1.p2 .p1 1.p2 .p1 Address Pipelining ·9.Fastest Read Cycles with Pipelined Address TimingTWO-BANK Interleaved Memory Address signal A2 selects bank Bit datapath to each bankFOUR-BANK Interleaved Memory Read and Write Cycles IntroductionXxxi Xxxix NON-PIPELINED AddressXxxxx Ixxxx Ixxx13 80386 Bus States not usIng pipelined address 3.3 NON·PIPELINED Address with Dynamic Data BUS Sizing ·14Asserting BS16# zero wait states, non·pipelinedaddress~~~~ DOO¥ Xixxxxx ValidXixxxx ,XXXXY BSI6# XXX XXx XXX X .. IXXXXwOO~ J, XXX XXX1/ \B516# ~~..tJ.~~~~~~~ BS16 # 44~~~...l-.lI...l Ready # 44~~.lI...l/l Bus Sizing with Pipelined AddressPipelined ~ ,T1-T~-T2PJ ,T1PT2PJ Idle non-pipelined pipelinedAcknowledge IO#, D/c# Ffi 20 Complete Bus States including pipelined addressXxixxy ~ /..XIXXY Xxxxy ~j XDONTCAR~X~ x~ ~X~~lKX~ /..XXXXXxxxx IXXXXIXXXXI.. /..DXXXIXXX ~ Xxxxiy ~ -XXIXXYInterrupt Acknowledge Inta Cycles ~--cp--- ----- ----- ----- ----- ~Halt Indication Cycle 23.Halt Indication CycleShutdown Indication Cycle 24. Shutdown Indication CycleOther Functional Descriptions Reset During Hold AcknowledgeBus Activity During and Following Reset Entering and Exiting Hold Acknowledge26. Requesting Hold from Active Bus NA # negated SELF-TEST Signature Component and Revision IdentifiersComponent Revision Component Revision Stepping Identifier NameSoftware Testing for Coprocessor Presence CMD1Mechanical Data Introduction PIN Assignment000 0 0 0 000 0 0 Vee Vss Package Dimensions and Mounting 1654189~1Package Thermal Specification Measure PGA Case TemperatureInfef80386 IllPower and Grounding Electrical DataD.C. Specifications Maximum Ratings1 A.C. Spec Definitions A.C. Specifications102 ·4 -16 A.C. Characteristics Symbol Parameter 80386-16 2 A.C. Specification TablesUnit Min Max Operating Frequency MHz Half of CLK2 Symbol Parameter Min 16 A.C. Characteristics Symbol Parameter80386-16 Min Unit Max 3 A.C. Test Loads 4 A.C. Timing Waveforms 80386 ~QW~OOg OOOIP@OOIMl~iiO@OO106 MAX Itm PI~ Instruction SET 80386 Instruction Encoding8o386Instructlon Set CIock Count Summary 111·1 Instruction Set Clock Count Summary 11280386 Instructlon Set CIockCount S ummary Contlnued RIm·1 80386 Instruction Set Clock Count Summary DoublewordInstruction Set Clock Count Summary 115Instruction Set Clock Count Summarycontlnued BIT ManipulationInstruction Set Clock Count Summar +ml 7+ml80386 Ins ruefIon SetCIoek CountSummary ConrInued Protected119 120 80386 Instructlon Set CIockCountSummaay Contmued Interrupt InstructionsO3861nstructlon Set CIockCount Summary Contlnued BoundInfef80386 80386 nstructlon Set CIockCount Summary ContlnuedNs ruetIon StCIe oekCount 5 ummary Contlnued MadearOverview ~~~\Field 2 32-Bit Extensions of the Instruction SetEncoding of Instruction Fields BitsEncoding of Address Mode 11010 OsbxOSBX+d16 EOIOS EAX Scale Factor NB/AE Encoding of Operation DirectionNAE NE/NZDomestic Sales Offices CaliforniaUnited States