Intel 80386 2 32-Bit Extensions of the Instruction Set, Encoding of Instruction Fields, Bits, 010

80386

8.2.232-Bit Extensions of the Instruction Set

With the 80386, the 86/186/286 instruction set is extended in two orthogonal directions: 32-bit forms of all 16-bit instructions are added to support the 32- bit data types, and 32-bit addressing modes are made available for all instructions referencing mem- ory. This orthogonal instruction set extension is ac- complished having a Default (D) bit in the code seg- ment descriptor, and by having 2 prefixes to the in- struction set.

Whether the instruction defaults to operations of 16 bits or 32 bits depends on the setting of the 0 bit in the code segment descriptor, which gives the de- fault length (either 32 bits or 16 bits) for both oper- ands and effective addresses when executing that code segment. In the Real Address Mode or Virtual 8086 Mode, no code segment descriptors are used, but a 0 value of 0 is assumed internally by the 80386 when operating in those modes (for 16-bit default sizes compatible with the 8086/80186/80286).

Two prefixes, the Operand Size Prefix and the Effec- tive Address Size Prefix, allow overriding individually the Default selection of operand size and effective address size. These prefixes may precede any op- code bytes and affect only the instruction they pre- cede. If necessary, one or both of the prefixes may be placed before the opcode bytes. The presence of the Operand Size Prefix and the Effective Address Prefix will toggle the operand size or the effective address size, respectively, to the value "opposite" from the Default setting. For example, if the default operand size is for 32-bit data operations, then pres- ence of the Operand Size Prefix toggles the instruc- tion to 16-bit data operation. As another example, if the default effective address size is 16 bits, pres- ence of the Effective Address Size prefix toggles the instruction to use 32-bit effective address computa- tions.

These 32-bit extensions are available in all 80386 modes, including the Real Address Mode or the Vir- tual 8086 Mode. In these modes the default is al- ways 16 bits, so prefixes are needed to specify 32- bit operands or addresses.

Unless specified otherwise, instructions with 8-bit and 16-bit operands do not affect the contents of the high-order bits of the extended registers.

8.2.3 Encoding of Instruction Fields

Within the instruction are several fields indicating register selection, addreSSing mode and so on. The exact encodings of these fields are defined immedi- ately ahead.

8.2.3.1ENCODING OF OPERAND LENGTH (w)

FIELD

For any given instruction performing a data opera- tion, the instruction is executing as a 32-bit operation or a 16-bit operation. Within the constraints of the operation size, the w field encodes the operand size as either one byte or the full operation size, as shown in the table below.

	Operand Size	Operand Size
wField	During 16·8it	During 32·8it
	Data Operations	Data Operations
0	8 Bits	8	Bits
1	16 Bits	32	Bits

8.2.3.2ENCODING OF THE GENERAL REGISTER (reg) FIELD

The general register is specified by the reg field, which may appear in the primary opcode bytes, or as the reg field of the "mod rim" byte, or as the rim field of the "mod rim" byte.

Encoding of reg Field When w Field

is not Present in Instruction

Register Selected Register Selected

reg Field During 16·8it During 32·8it Data Operations Data Operations

000	AX	EAX
001	CX	ECX
010	OX	EDX
011	BX	EBX
100	SP	ESP
101	BP	EBP
101	SI	ESI
101	01	EDI

Encoding of reg Field When w Field

is Present in Instruction

Register Specified by reg Field

During 16·8itData Operations:

reg	Function of w Field
	(when w = 0)	(when w = 1)
000	AL	AX
001	CL	CX
010	DL	OX
011	BL	BX
100	AH	SP
101	CH	BP
110	DH	SI
111	BH	01

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