5.FUNCTIONAL DATA (Continued)

 

 

 

5.4.3.4

Pipelined Address

80

 

5.4.3.5

Initiating and Maintaining Pipelined Address

82

 

5.4.3.6

Pipelined Address with Dynamic Data Bus Sizing

84

 

5.4.4

Interrupt Acknowledge (INTA) Cycles

86

 

5.4.5

Halt Indication Cycle

87

 

5.4.6

Shutdown Indication Cycle

88

 

5.5

Other Functional Descriptions

89

 

5.5.1

 

Entering and Exiting Hold Acknowledge

89

 

5.5.2

Reset during Hold Acknowledge

89

 

5.5.3

Bus Activity During and Following Reset

89

 

5.6

Self-test Signature

91

 

5.7

Component and Revision Identifiers

91

 

5.8

Coprocessor Interface

93

 

5.8.1

 

Software Testing for Coprocessor Presence

93

6.

MECHANICAL DATA

94

 

6.1

Introduction

94

 

6.2

Pin Assignment

94

 

6.3

Package Dimensions and Mounting

97

 

6.4

Package Thermal Specification

98

7.

ELECTRICAL DATA

100

 

7.1

Introduction

100

 

7.2

Power and Grounding

100

 

7.2.1

 

Power Connections

100'

 

7.2.2

Power Decoupling Recommendations

100

 

7.2.3

Resistor Recommendations

100

 

7.2.4

Other Connection Recommendations

100

 

7.3

Maximum Ratings

101

 

7.4

D.C. Specifications

101

 

7.5

A.C. Specifications

102

 

7.5.1

A.C. Spec Definitions

102

 

7.5.2

A.C. Specification Tables

103

 

7.5.3

A.C. Test Loads

105

 

7.5.4

A.C. Timing Waveforms

105

 

7.6

Designing for ICE-386 Use

108

8.

INSTRUCTION SET

110

 

8.1

Instruction Encoding and Clock Count Summary

110

 

8.2

Instruction Encoding Details

125

 

8.2.1

Overview

125

 

8.2.2

32-Bit Extensions of the Instruction Set

126

 

8.2.3

Encoding of Instruction Fields

126

 

8.2.3.1

Encoding of the Operand Length (w) Field

126

 

8.2.3.2

Encoding of the General Register (reg) Field

126

 

8.2.3.3

Encoding of the Segment Register (sreg) Field

127

 

8.2.3.4

Encoding of Address Mode

127

 

8.2.3.5

Encoding of Operation Direction (d) Field

131

 

8.2.3.6

Encoding of Sign-extend (s) Field

131

 

8.2.3.7

Encoding of Conditional Test (tUn) Field

131

 

8.2.3.8

Encoding of Control or Debug or Test Register (eee) Field

131

NOTE

This is revision 002; This supercedes all previous revisions.

6

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Intel 80386 manual 3.4, Initiating and Maintaining Pipelined Address, Pipelined Address with Dynamic Data Bus Sizing, 127