Intel 80386 manual Segment Registers Descriptor Registers Loaded Automatically

inter80386

OF (Overflow Flag, bit 11)

OF is set if the operation resulted in a signed overflow. Signed overflow occurs when the operation resulted in carry/borrow into the sign bit (high-order bit) of the result but did not result in a carry/borrow out of the high- order bit, or vice-versa. For 8/16/32 bit oper- ations, OF is set according to overflow at bit 7/15/31, respectively.

DF (Direction Flag, bit 10)

DF defines whether ESI and/or EDI registers postdecrement or postincrement during the string instructions. Postincrement occurs if DF is reset. Postdecrement occurs if DF is set.

IF (INTR Enable Flag, bit 9)

The IF flag, when set, allows recognition of external interrupts signalled on the INTR pin. When IF is reset, external interrupts signalled on the INTR are not recognized. IOPL indi- cates the maximum CPL value allowing alter- ation of the IF bit when new values are popped into EFLAGS or FLAGS.

TF (Trap Enable Flag, bit 8)

TF controls the generation of exception 1 trap when single-stepping through code. When TF is set, the 80386 generates an ex- ception 1 trap after the next instruction is exe- cuted. When TF is reset, exception 1 traps occur only as a function of the breakpoint ad- dresses loaded into debug registers DRO- DR3.

SF (Sign Flag, bit 7)

SF is set if the high-order bit of the result is set, it is reset otherwise. For 8-, 16-, 32-bit operations, SF reflects the state of bit 7, 15, 31 respectively.

ZF (Zero Flag, bit 6)

ZF is set if all bits of the result are O. Other- wise it is reset.

AF (Auxiliary Carry Flag, bit 4)

The Auxiliary Flag is used to simplify the addi- tion and subtraction of packed BCD quanti- ties. AF is set if the operation resulted in a carry out of bit 3 (addition) or a borrow into bit 3 (subtraction). Otherwise AF is reset. AF is affected by carry out of, or borrow into bit 3 only, regardless of overall operand length: 8, 16 or 32 bits.

PF (Parity Flags, bit 2)

PF is set if the low-order eight bits of the op- eration contains an even number of "1 's" (even parity). PF is reset if the low-order eight bits have odd parity. PF is a function of only the low-order eight bits, regardless of oper- and size.

CF (Carry Flag, bit 0)

CF is set if the operation resulted in a carry out of (addition), or a borrow into (subtraction) the high-order bit. Otherwise CF is reset. For 8-, 16- or 32-bit operations, CF is set accord- ing to carry/borrow at bit 7, 15 or 31, respec- tively.

Note in these descriptions, "set" means "set to 1," and "reset" means "reset to 0."

2.3.4 Segment Registers

Six 16-bit segment registers hold segment selector values identifying the currently addressable memory segments. Segment registers are shown in Figure 2-

4.In Protected Mode, each segment may range in size from one byte up to the entire linear and physi-

SEGMENT
REGISTERS			DESCRIPTOR REGISTERS (LOADED AUTOMATICALLY)
A	\		A			\
(		(		Other
				Segment
15	0		Physical Base Address Segment Limit	Attributes from Descriptor
Selector		CS-		-	-
Selector		SS-				-
Selector		DS-		-	-	-
Selector		ES-		-	-	-
Selector		FS-		-	-	-
Selector		GS-		-	-	-

Figure 2-4.80386 Segment Registers, and Associated Descriptor Registers

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