80386

At the end of the second bus state within the bus cycle, READY # is sampled. At that time, if external hardware acknowledges the bus cycle by asserting READY #, the bus cycle terminates as shown in Fig- ure 5-11. If READY # is negated as in Figure 5-12, the cycle continues another bus state (a wait state) and READY # is sampled again at the end of that state. This continues indefinitely until the cycle is ac- knowledged by READY # asserted.

When the current cycle is acknowledged, the 80386 terminates it. When a read cycle is acknowledged, the 80386 latches the information present at its data pins. When a write cycle is acknowledged, the 80386 write data remains valid throughout phase one of the next bus state, to provide write data hold time.

5.4.3.2 NON-PIPELINED ADDRESS

Any bus cycle may be performed with non-pipelined address timing. For example, Figure 5-11 shows a mixture of read and write cycles with non-pipelined

address timing. Figure 5-11 shows the fastest possi- ble cycles with non-pipelined address have two bus states per bus cycle. The states are named T1 and T2. In phase one of the T1, the address signals and bus cycle definition signals are driven valid, and to signal their availability, address status (ADS#) is simultaneously asserted.

During read or write cycles, the data bus behaves as follows. If the cycle is a read, the 80386 floats its data signals to allow driving by the external device being addressed. If the cycle is a write, data signals are driven by the 80386 beginning in phase two of T1 until phase one of the bus state following cycle acknowledgment.

Figure 5-12 illustrates non-pipelined bus cycles with one wait added to cycles 2 and 3. READY# is sam- pled negated at the end of the first T2 in cycles 2 and 3. Therefore cycles 2 and 3 have T2 repeated. At the end of the second T2, READY # is sampled asserted.

,/

/

/

 

IDLE

I

CYCLE 1

I

CYCLE 2

 

 

CYCLE 3

 

 

 

 

NON-PIPElINED

NON-PIPELINED

 

NON-PIPELINED

 

 

 

 

(READ)

 

(WRITE)

 

 

 

(READ)

 

 

 

n

 

Tl

T2

T1

T2

T2

n

T1

T2

T2

Ti

ClK2 [ - rutrutrutrutil..fl ilJl..nn.nnrut1.flrut

(82384 elK) [

-VV V V \J\J\fV \J\JV

8EO#-8El # [

X XX

IX

VALID 1

IX

VALID 2

 

XXXXX

 

 

IXXXX

A2-A31.

 

VALID 3

 

M/IO N,D/CN

 

 

 

 

 

 

 

 

 

 

 

 

W/R# [

XXXI),

 

 

/

 

 

,,(XXXIX.

 

 

~

ADSN [

 

i' - r-

"-.-1

 

 

~/

 

 

 

 

 

 

 

 

 

 

 

 

 

 

NA# [

IXXX

IX XXX XXXX XXXXy "(

XXX

XX

IXXX

~XXXXIXXXX

 

 

 

52-BIT

 

 

52-BIT

 

 

 

52-BIT

 

 

 

BuStZE

 

 

BUStZE

 

 

 

BUStZE

8516 # [

XIXXXXIXXXXY

~XXXXxXXX rY "(IXXXXIXXX)( XXXXrY

'<~

READYN [

XXXXX IXXXX XXA

.(XXIXXY

~ .(XXIXXXX XXrY ~ n:x

 

 

 

 

END CYCLE 1

 

END CYCLE 2

 

 

END CYCLE 3

lOCK # [

XX

 

VALID 1

IX

VALID 2

 

IXXX

 

VALID 3

 

IXXXX

00- 031 [

. ----------~--¢<

OUT

 

}---------

----

--¢---

231630-16

Idle states are shown here for diagram variety only. Write cycles are not always followed by an idle state. An active bus cycle can immediately follow the write cycle.

Figure 5·12.Various Bus Cycles and Idle States with Non-Pipelined Address

(various number of wait states)

76

Page 137
Image 137
Intel 80386 manual NON-PIPELINED Address, Xxxi Xxxix, XXX Ixxx, Xixxxxixxxxy, Xxxxx Ixxxx XXA Xxixxy