Motorola MVME5100 manuals

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Motorola MVME5100 Manual

Motorola MVME5100 Manual

168 pages1.19 Mb

3Safety Summary
- Ground the Instrument.
- Do Not Operate in an Explosive Atmosphere.
- Keep Away From Live Circuits Inside the Equipment.
- Use Caution When Exposing or Handling a CRT.
- Do Not Substitute Parts or Modify Equipment.
- Observe Warnings in Manual.
- Warning
Flammability
4!
- EMI Caution
!
- Lithium Battery Caution
- 5CE Notice (European Community)
- Notice
- 6Limited and Restricted Rights Legend
7Contents
11List of Figures
13List of Tables
15About This Manual
- 17Summary of Changes
- Overview of Contents
- 19Comments and Suggestions
- Conventions Used in This Manual
  - 20Terminology
211Hardware Preparation and Installation
- Getting Started
  - Overview and Equipment Requirements
  - 22Unpacking Instructions
- 23Preparation
  - Hardware Configuration
  - 25Jumper Settings
  - 26Installation Considerations
- 28Installation
  - Installation
    - P1 P2
  - 29Figure 1-1. MVME5100 Layout
    - http://www.motorola.com/computer/literature 1-9
  - 30PMC Modules
  - 32Primary PMCspan
  - 34Secondary
  - PMCspan
  - 36MVME5100
392Operation
- Switches and Indicators
  - ABT/RST Switch
  - 40Status Indicators
  - Connectors
- 41System Powerup
  - 42Initialization Process
453PPCBug Firmware
- PPCBug Overview
  - Implementation and Memory Requirements
- 47Using PPCBug
  - 48Hardware and Firmware Initialization
- 50Default Settings
  - 51CNFG - Configure Board Information Block
  - ENV - Set Environment
  - 60LED/Serial Startup Diagnostic Codes
  - 61Configuring the VMEbus Interface
  - 65Firmware Command Buffer
- 66Standard Commands
  - 70Diagnostics
734Functional Description
- Features Summary
  - 74Table 4-1. MVME5100 General Features (Continued)
- 75Features Descriptions
  - General
    - 4-4 Computer Group Literature Center Web Site
    - Functional Description
      - Local Bus
      - 33MHz 32/64-bit PCI
      - VME P2
      - PCI Expansion
        VME P1
    - 76The following diagram illustrates the architecture of the MVME5100 Single Board Computer.
    - Figure 4-1. MVME5100 Block Diagram
  - 77Processor
  - System Memory Controller and PCI Host Bridge
  - Memory
  - 79P2 Input/Output (I/O) Modes
  - Input/Output Interfaces
835Pin Assignments
- Summary
  - The following tables summarize all of the jumpers and connectors:
- 84Jumper Settings
- 85Connectors
  - IPMC761 Connector (J3) Pin Assignments
  - 86Memory Expansion Connector (J8) Pin Assignments
    - 87Table 5-3. Memory Expansion Connector Pin Assignments (Continued)
  - 89PCI Expansion Connector (J25) Pin Assignments
    - GND
    - 90+5V
    - 91GND
  - 92PCI Mezzanine Card (PMC) Connectors
    - 93Table 5-5. PMC Slot 1 Connector (J11) Pin Assignments (Continued)
    - 94Table 5-6. PMC Slot 1 Connector (J12) Pin Assignments
    - 95
    - Table 5-7. PMC Slot 1 Connector (J13) Pin Assignments
    - Table 5-6. PMC Slot 1 Connector (J12) Pin Assignments (Continued)
    - 96Table 5-7. PMC Slot 1 Connector (J13) Pin Assignments (Continued)
    - 97Table 5-8. PMC Slot 1 Connector (J14)
    - 99Table 5-9. PMC Slot 2 Connector (J21) Pin Assignments
    - 100Table 5-10. PMC Slot 2 Connector (J22) Pin Assignments
    - Table 5-9. PMC Slot 2 Connector (J21) Pin Assignments (Continued)
    - 101Table 5-10. PMC Slot 2 Connector (J22) Pin Assignments (Continued)
    - 102Table 5-11. PMC Slot 2 Connector (J23) Pin Assignments
    - 103Table 5-12. PMC Slot 2 Connector (J24) Pin Assignments
    - Table 5-11. PMC Slot 2 Connector (J23) Pin Assignments (Continued)
    - 104Table 5-12. PMC Slot 2 Connector (J24) Pin Assignments (Continued)
  - 105VMEbus Connectors P1 & P2 Pin Assignments (PMC mode)
    - 106Table 5-13. VMEbus Connector P2 Pin Assignments (PMC Mode) (Continued)
  - 107VMEbus P1 & P2 Connector Pin Assignments (SBC Mode)
    - 108Table 5-14. VMEbus P2 Connector Pinouts with IPMC761- SBC Mode (Continued)
  - 11110 BaseT/100 BaseTx Connector Pin Assignments
  - 112COM1 and COM2 Connector Pin Assignments
1136Programming the MVME51xx
- Memory Maps
  - 114Processor Bus Memory Map
  - 117PCI Local Bus Memory Map
  - VMEbus Memory Map
- 118Programming Considerations
  - PCI Arbitration
    - 6-8 Computer Group Literature Center Web Site
    - Programming the MVME51xx
    - 120Figure 6-1. VMEbus Master Mapping
      - VMEBUS
      - PCI MEMORYPROCESSOR
  - 121Interrupt Handling
    - 122Figure 6-2. MVME510x Interrupt Architecture
  - 123DMA Channels
  - Sources of Reset
  - 125Endian Issues
127A
- ASpecifications
  - General Specifications
    - A
  - 128Power Requirements
    - A
  - 129Cooling Requirements
  - EMC Compliance
131B
- BTroubleshooting
  - Solving Startup Problems
135C
- CRelated Documentation
  - Motorola Computer Group Documents
  - 136Manufacturers Documents
    - 137Table C-2. Manufacturers Documents (Continued)
  - 138Related Specifications
139D
- DRAM500 Memory Expansion
- Module
  - Overview
  - Features
  - 140Functional Description
    - RAM500 Description
      - Functional Description
        Bottom-side MVME5100-MEZ Connector
      - 142Figure D-1. RAM500 Block Diagram
        D-4 Computer Group Literature Center Web Site
        Top-side MVME5100-MEZ Connector
        1 Bank of 9 (x8)
    - SROM
    - Host Clock Logic
  - 143RAM500 Module Installation
  - 145RAM500 Connectors
    - Bottom Side Memory Expansion Connector (P1)
      - 147Table D-3. RAM500 Bottom Side Connector (P1)
    - 148Top Side Memory Expansion Connector (J1)
      - 150Table D-4. RAM500 Top Side Connector (J1)
  - 151RAM500 Programming Issues
    - Serial Presence Detect (SPD) Data
153E
- EThermal Analysis
  - Thermally Significant Components
    - E-4 Computer Group Literature Center Web Site
    - Thermal Analysis
      - P1 P2
    - 156Figure E-1. Thermally Significant Components on the MVME5100 Single Board Computer - Primary Side
      - Thermally Significant Components
        2844 1100
      - http://www.motorola.com/computer/literature E-5
    - 157Figure E-2. Thermally Significant Components on the IPMC761 Module - Primary Side
    - IPMC761
  - 158Component Temperature Measurement
    - Preparation
    - Measuring Junction Temperature
    - Measuring Case Temperature
      - 160Figure E-3. Mounting a Thermocouple Under a Heatsink
    - 161Measuring Local Air Temperature
  - 163Index
    - A
    - B
    - as power source
    - C
    - D
    - 164E
    - F
    - G
    - H
    - 165I
    - J
    - L
    - M
    - N
    - 166O
    - P
    - 167R
    - S
    - 168T
    - U
    - V
    - W

Motorola MVME5100 Manual

330 pages1.39 Mb

3Safety Summary
- Ground the Instrument.
- Do Not Operate in an Explosive Atmosphere.
- Keep Away From Live Circuits Inside the Equipment.
- Use Caution When Exposing or Handling a CRT.
- Do Not Substitute Parts or Modify Equipment.
- Observe Warnings in Manual.
- Warning
Flammability
4!
- EMI Caution
!
- Lithium Battery Caution
- 5CE Notice (European Community)
- Notice
- 6Limited and Restricted Rights Legend
7Contents
15List of Figures
17List of Tables
21About This Manual
- 24Summary of Changes
- Overview of Contents
- 25Comments and Suggestions
- Conventions Used in This Manual
  - 26Terminology
291Product Data and Memory Maps
- 30Table 1-1. MVME Key Features (Continued)
  - Introduction
  - http://www.motorola.com/computer/literature 1-3
- 31The following block diagram illustrates the architecture of the MVME5100 Single Board Computer.
  - Local Bus
  - 33 MHz 32/64-bit PCI
  - VME P2
  - PCI Expansion
    - VME P1
- Figure 1-1. MVME5100 Block Diagram
- 32Memory maps
  - Processor Memory Map
  - PCI Local Bus Memory Map
  - VMEbus Memory Map
- 36System Bus
  - 37Processors
  - Processor Type Identification
  - Processor PLL Configuration
  - L2 Cache
  - 38L2 Cache SRAM Size
  - Cache Speed
  - FLASH Memory
  - 39ECC Memory
  - P2 I/O Modes
  - Serial Presence Detect (SPD) Definitions
- 40Hawk ASIC
  - 41Hawk I2C interface and configuration information
  - 42Vital Product Data (VPD) and Serial Presence Detect (SPD) Data
- 43PCI Local Bus
  - PCI Arbitration Assignments for Hawk ASIC
  - 44The Ethernet Controller
  - 45PMC/PCI Expansion Slots
  - The Universe ASIC
    - 1-18 Computer Group Literature Center Web Site
    - Product Data and Memory Maps
    - 46Figure 1-2. VMEbus Master Mapping
      - VMEBUS
      - PCI MEMORYPROCESSOR
  - 47PCI Configuration Space
  - 49Hawk External Register Bus Address Assignments
    - 50Table 1-9. Hawk External Register Bus Summary (Continued)
  - 51Dual TL16C550 UARTs
  - 52Status Register
  - 53MODFAIL Bit Register
  - 54MODRST Bit Register
  - 55TBEN Bit Register
  - 56NVRAM/RTC & Watchdog Timer
  - 57Software Readable Header/Switch Register (S1)
    - ON ON
  - 58Geographical Address Register (VME board)
  - 59Extended Features Register 1
  - 60Board Last Reset Register
  - 61Extended Features Register 2
- 62IPMC7xx ISA Bus Resources
  - W83C554 PIB Registers
  - PC87308VUL Super I/O (ISASIO) Strapping
  - 63Z85230 ESCC and Z8536 CIO Registers and Port Pins
  - 67ISA DMA Channels
692Hawk PCI Host Bridge & Multi- Processor Interrupt Controller
- Overview
- Features
  - Block Diagram
  - http://www.motorola.com/computer/literature 2-3
- 71Block Diagram
  - Figure 2-1. Hawk PCI Host Bridge Block Diagram
    - PCI Host Bridge (PHB) PCI Bus PPC60x Bus
- 72Functional Description
  - Architectural Overview
  - 73PPC Bus Interface
  - 87PCI Bus Interface
  - 106Endian Conversion
    - 107Functional Description
    - http://www.motorola.com/computer/literature 2-39
  - 109Error Handling
  - 110Watchdog Timers
    - 112Table 2-14. WDTxCNTL Programming
  - 113PCI/PPC Contention Handling
  - 116Transaction Ordering
  - 117PHB Hardware Configuration
- 119Multi-Processor Interrupt Controller (MPIC)
  - MPIC Features:
  - Architecture
  - 120External Interrupt Interface
  - 122Processors Current Task Priority
  - Nesting of Interrupt Events
  - Spurious Vector Generation
  - 123Interprocessor Interrupts (IPI)
  - 8259 Compatibility
  - Hawk Internal Errror Interrupt
  - 124Timers
  - Interrupt Delivery Modes
  - 125Block Diagram Description
    - 126Figure 2-9. MPIC Block Diagram
  - 130Programming Notes
  - 132Operation
  - 134Architectural Notes
  - Effects of Interrupt Serialization
- 135Registers
  - 136PPC Registers
    - The PPC register map of the PHB is shown in Table 2-16. Table 2-16. PPC Register Map for PHB
    - 137Table 2-16. PPC Register Map for PHB (Continued)
    - 138Vendor ID/Device ID Registers
    - 139Registers
    - http://www.motorola.com/computer/literature 2-71
    - Reset
    - Operation
    - Address $FEFF0008 Bit
    - Name GCSR
    - 154If the PSMA or PRTA bit are set, the register is defined by the following table:
    - 163Registers
    - http://www.motorola.com/computer/literature 2-95
    - 164WDTxSTAT Registers
  - 165PCI Registers
    - 166Vendor ID/ Device ID Registers
    - Table 2-18. PCI I/O Register
    - 169Revision ID/ Class Code Registers
    - 170MPIC I/O Base Address Register
    - 175Conceptual perspective from the PCI bus:
    - Perspective from the PPC bus in Big Endian mode:
    - Perspective from the PPC bus in Little Endian mode:
    - 177Perspective from the PPC bus in Big Endian mode:
    - Perspective from the PPC bus in Little Endian mode:
  - 178MPIC Registers
1973System Memory Controller (SMC)
- Overview
- Bit Ordering Convention
- Features
- 198Block Diagrams
  - PPC60x Bus
  - DRAM Synch HAWK Check
  - Data
    - Block Diagrams
    - Figure 3-2. Hawks System Memory Controller Internal Data Paths
      - http://www.motorola.com/computer/literature 3-3
        SDRAM PowerPC Side Side
199+ +
- 200Figure 3-3. Overall SDRAM Connections (4 Blocks using Register Buffers)
  - 3-4 Computer Group Literature Center Web Site
    - HAWK
  - Block Diagrams
    - PPC60x Data MEM Data
- 201Figure 3-4. Hawks System Memory Controller Block Diagram
  - http://www.motorola.com/computer/literature 3-5
    - MEM Addr PPC60x Addr
    - Bus
- I2C
  - PPC60x Attr
  - PPC60x Ctrl MEM Ctrl
- 202Functional Description
  - SDRAM Accesses
  - 205SDRAM Organization
  - PPC60x Bus Interface
  - 207SDRAM ECC
    - 2083-12 Computer Group Literature Center Web Site
    - Error Type Single-Beat/Four- Beat Read Single-Beat Write Four-Beat Write Scrub Single-Bit Error
    - Double-Bit Error
    - Triple- (or greater) Bit Error
  - 210ROM/Flash Interface
    - 212Table 3-3. PPC60x to ROM/Flash (16 Bit Width) Address Mapping
    - 213Table 3-4. PPC60x to ROM/Flash (64 Bit Width) Address Mapping
    - 216Table 3-6. PPC60x Bus to ROM/Flash Access Timing (80ns @ 100 MHz)
    - Table 3-7. PPC60x Bus to ROM/Flash Access Timing (50ns @ 100 MHz)
  - 218I2C Interface
    - 220Figure 3-5. Programming Sequence for I2C Byte Write
      - (*)
      - 3-24 Computer Group Literature Center Web Site
    - 222Figure 3-6. Programming Sequence for I2C Random Read
      - 3-26 Computer Group Literature Center Web Site
        d
        (*)
    - 224Figure 3-7. Programming Sequence for I2C Current Address Read
      - 3-28 Computer Group Literature Center Web Site
        (*)
    - 226Figure 3-8. Programming Sequence for I2C Page Write
      - 3-30 Computer Group Literature Center Web Site
        * **
        (*)
      - Functional Description
    - 229Figure 3-9. Programming Sequence for I2C Sequential Read
      - http://www.motorola.com/computer/literature 3-33
        (*)
  - 230Refresh/Scrub
  - CSR Accesses
  - External Register Set
  - Chip Configuration
- 231Programming Model
  - CSR Architecture
    - 3-36 Computer Group Literature Center Web Site
  - 232Register Summary
    - Table 3-9 shows a summary of the internal and external register set. Table 3-9. Register Summary
    - 233Table 3-9. Register Summary (Continued)
      - http://www.motorola.com/computer/literature 3-37
  - 234Detailed Register Bit Descriptions
    - http://www.motorola.com/computer/literature 3-39
    - 235Vendor/Device Register
    - http://www.motorola.com/computer/literature 3-41
    - 237SDRAM Enable and Size Register (Blocks A, B, C, D)
    - 3-46 Computer Group Literature Center Web Site
    - 242ECC Control Register
    - 3-52 Computer Group Literature Center Web Site
    - 248Error_Address Register
    - 255http://www.motorola.com/computer/literature 3-59
    - 258Data Parity Error Address Register
    - 259Data Parity Error Lower Data Register
    - 260I2C Clock Prescaler Register
    - http://www.motorola.com/computer/literature 3-67
    - 263I2C Receiver Data Register
      - ram h siz2
      - ram h siz1
      - ram h siz0
      - ram h en
      - ram g siz3
      - ram g siz2
      - ram g siz1
      - ram g siz0
      - ram g en
      - ram f siz3
      - ram f siz2
      - ram f siz1
      - ram f siz0
      - ram f en
      - ram e siz3
      - ram e siz2
      - ram e siz1
      - ram e siz0
      - ram e en
    - Address Bit
    - Name Operation Reset
    - Address Bit
    - Name
      - ram h siz3
    - Operation
    - Reset
    - 26932-Bit Counter
- 271Software Considerations
  - Programming ROM/Flash Devices
  - Writing to the Control Registers
  - 272Initializing SDRAM Related Control Registers
    - 3-80 Computer Group Literature Center Web Site
    - 276Table 3-18. Deriving tras, trp, trcd and trc Control Bit Values from SPD Information (Continued)
- 283ECC Codes
  - 284Table 3-22. Single Bit Errors Ordered by Syndrome Code
- 2854Hawk Programming Details
  - PCI Arbitration
    - Hawk MPIC External Interrupts
    - 2878259 Interrupts
      - 288Table 4-2. PBC ISA Interrupt Assignments (Continued)
  - 289Exceptions
    - Sources of Reset
    - Soft Reset
    - CPU Reset
    - 290Error Notification and Handling
  - 291Endian Issues
    - 4-8 Computer Group Literature Center Web Site
    - Hawk Programming Details
    - 292Figure 4-2. Little-Endian Mode
295A
- ARelated Documentation
  - Motorola Computer Group Documents
  - 296Manufacturers Documents
    - 297Table A-2. Manufacturers Documents (Continued)
  - 298Related Specifications
299B
- BMVME5100 VPD Reference Information
  - Vital Product Data (VPD) Introduction
    - How to Read the VPD Information
    - 300B
    - How to Modify the VPD Information
    - 301What Happens if the VPD Information is Corrupted?
    - How to Fix Corrupted VPD Information
    - What if Your Board Has the Wrong VPD?
    - How to Fix Wrong VPD Problems
    - 302B
    - VPD Definitions - Packet Types
      - 303Table B-1. VPD Packet Types (Continued)
    - 305VPD Definitions - Product Configuration Options Data
      - 306Table B-2. MCG Product Configuration Options Data (Continued)
    - 307VPD Definitions - FLASH Memory Configuration Data
      - A product may contain multiple FLASH memory configuration packets.
      - Table B-3. FLASH Memory Configuration Data
    - 308BVPD Definitions - L2 Cache Configuration Data
      - 309Table B-4. L2 Cache Configuration Data (Continued)
    - 310BVPD Definitions - VPD Revision Data
      - Vital Product Data (VPD) Introduction
      - http://www.motorola.com/computer/literature B-13
      - 311SROM_CRC.C
        312B-14 Computer Group Literature Center Web Site
        MVME5100 VPD Reference Information
    - 314B
315C
- CVMEbus Mapping Example
  - 317C
- 319Index
  - Numerics
  - A
  - SMC
  - B
  - 320C
  - D
  - 321E
  - F
  - G
  - 322H
  - I
  - 323L
  - M
  - N
  - O
  - P
  - 325R
  - 326Address Parity Error Address
  - 327S
  - 328T
  - U
  - V
  - 329W
  - Z

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