Motorola MVME5100 Table 3-6. PPC60x Bus to ROM/Flash Access Timing (80ns @ 100 MHz), Table 3-7. PPC60x Bus to ROM/Flash Access Timing (50ns @ 100 MHz)

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System Memory Controller (SMC)
3
Notes The information in Table 3-6 applies to access timing when
configured for devices with an access time equal to 8 clock
periods.
Table 3-6. PPC60x Bus to ROM/Flash Access Timing
(80ns @ 100 MHz)
ACCESS TYPE
CLOCK PERIODS REQUIRED FOR: Total
Clocks
1st Beat 2nd Beat 3rd Beat 4th Beat
16
Bits 64 Bits 16 Bits 64 Bits 16 Bits 64 Bits 16 Bits 64 Bits 16 Bits 64 Bits
4-Beat Read 54 18 48 12 48 12 48 12 198 54
4-Beat Write N/A N/A
1-Beat Read (1 byte)1818------1818
1-Beat Read (2 to 8
bytes) 5418------5418
1-Beat Write 2121------2121
Table 3-7. PPC60x Bus to ROM/Flash Access Timing
(50ns @ 100 MHz)
ACCESS TYPE
CLOCK PERIODS REQUIRED FOR: Total
Clocks
1st Beat 2nd Beat 3rd Beat 4th Beat
16
Bits 64 Bits 16 Bits 64 Bits 16 Bits 64 Bits 16 Bits 64 Bits 16 Bits 64 Bits
4-Beat Read 42 15 36 9 36 9 36 9 150 42
4-Beat Write N/A N/A
1-Beat Read (1 byte)1515------1515
1-Beat Read (2 to 8
bytes) 4215------4215
1-Beat Write 2121------2121