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Product Data and Memory Maps
1
The following sections describe the memory maps for the MVME5100.
Processor Memory Map
The processor memory map configuration is under the control of the PCI
Host Bridge (PHB) and System Memory Controller (SMC) portions of the
Hawk ASIC. The Hawk adjusts system mapping to suit a given
application via programmable map decoder registers. At system power-up
or reset, a default processor memory map ta kes over.
Following a reset, the memory map presented to the processor is identical
to the CHRP memory map described in this document.
The MVME5100 is fully capable of supporting both the PREP and the
CHRP processor memory maps with ROM/FLASH size limited to 16MB
and RAM size limited to 2GB.
Default Processor Memory Map
The default processor memory map that is valid at power-up or reset
remains in effect until reprogrammed for spe cific applications. Table 1-2
defines the entire default map ($00000000 to $FFFFFFFF).
Table 1-2. Default Processor Memory Map
Processor Address Size Definition
Start En d
0000 0000 7FFF FFFF 2GB Not Mapped
8000 0000 8080 FFFF 8M+64K Zero-based PCI/ISA I/O Space
8081 0000 FEF7 FFFF 2GB-24MB-576KB Not Mapped
FEF8 0000 FEF8 FFFF 64KB System Memory Controller Registers