3-2 Computer Group Literature Center Web Site
System Memory Controller (SMC)
3
❏ROM/Flash Interface
– Two blocks with each block being 16 or 64 bits wide.
– Programmable access time on a per-block basis.
❏I2C master interface.
❏External status/control register support
Block Diagrams
Figure 3-1 depicts a Hawk as it would be connected with SDRAMs in a
system. Figure 3-2 shows the SMC’s internal data paths. Figure 3-3 shows
the overall SDRAM connections. Figure 3-4 shows a block diagram of the
SMC portion of the Hawk ASIC.
Figure 3-1. Hawk Used with Synchronous DRAM in a System

PPC60x Bus

DRAM

Synch

HAWK

Check

Data

PowerPC
Data (64 Bits)
PowerPC
SDRAM
Data (64 Bits)
SDRAM
Address & Control
SDRAM
Check Bits (8 Bits)
Address &Control
PowerPC
Data Parity (8 Bits)
PowerPC
Address Parity (4 bits)