Motorola MVME5100 If the PSMA or PRTA bit are set, the register is defined by the following table:

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Hawk PCI Host Bridge & Multi-Processor Interrupt Controller
2
If the PSMA or PRTA bit are set, the register is defined by the following
table:
WP Write Post Completion. This bit is set when the P CI
master detects an error while completing a write post
transfer.
XIDx PPC Master ID. This field contains the ID of the PPC
master which originated the transfer in whic h the error
occurred. The encoding scheme is identical to that used in
the GCSR register.
COMMx PCI Command. This field contains the PCI command of
the PCI transfer in which the error occurred.
BYTEx PCI Byte Enable. This field contains the PCI byte
enables of the PCI transfer in which the e rror occurred. A
set bit designates a selected byte.
Address $FEFF002C
Bit 01234567891
01 11 21 31 41 51 61 71 81 92 02 12 22 32 42 52 62 72 82 93 03 1
Name EATTR
WP MID1 MID0 COMM3 COMM2 COMM1 COMM0 BYTE7 BYTE6 BYTE5 BYTE4 BYTE3 BYTE2 BYTE1 BYTE0
Operation R R
R R R R R R R R R R R R R R R R
Reset $00 $00
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0