Registers
http://www.motorola.com/computer/literature 2-99
2
PCI Command/ Status RegistersThe Command Register (COMMAND) provides coarse control over the PHB ability to generate and respond to PCI cycles. The bits within the COMMAND register are defined as follows:IOSP IO Space Enable. If set, the PHB will respond to PCI I/O accesses when appropriate. If cleared, the PHB will not respond to PCI I/O space accesses.MEMSP Memory Space Enable. If set, the PHB will respond to PCI memory space accesses when appropriate. If cleared, the PHB will not respond to PCI memory space accesses.MSTR Bus Master Enable. If set, the PHB may act as a master on PCI. If cleared, the PHB may not act as a PCI Master.PERR Parity Error Response. If set, the PHB will check parity on all PCI transfers. If cleared, the PHB will ignore any parity errors that it detects and continue normal operati on.SERR System Error Enable. This bit e nables the SERR_ output pin. If clear, the PHB will never drive SERR_. If set, the PHB will drive SERR_ active when a system error is detected.Offset $04
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name STATUS COMMAND
RCVPE
SIGSE
RCVMA
RCVTA
SIGTA
SELTIM1
SELTIM0
DPAR
FAST
P66M
SERR
PERR
MSTR
MEMSP
IOSP
Operation
R/C
R/C
R/C
R/C
R/C
R
R
R/C
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R/W
R
R/W
R
R
R
R/W
R/W
R/W
Reset
0
0
0
0
0
0
1
0
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0