ix
PCI Slave...................................................................................................2-22
PCI FIFO...................................................................................................2-26
PCI Master.................................................................................................2-26
Generating PCI Cycles..............................................................................2-29
PCI Arbiter................................................................................................2-34
Endian Conversion............................................................................................2-38
When PPC Devices are Big-Endian..........................................................2-38
When PPC Devices are Little Endian........................................................2-39
PHB Registers............................................................................................2-40
Error Handling..................................................................................................2-41
Watchdog Timers..............................................................................................2-42
PCI/PPC Contention Handling.........................................................................2-45
Transaction Ordering........................................................................................2-48
PHB Hardware Configuration..........................................................................2-49
Multi-Processor Interrupt Controller (MPIC)..........................................................2-51
MPIC Features:.................................................................................................2-51
Architecture......................................................................................................2-51
External Interrupt Interface...............................................................................2-52
CSR’s Readability.............................................................................................2-53
Interrupt Source Priority...................................................................................2-53
Processor’s Current Task Priority.....................................................................2-54
Nesting of Interrupt Events...............................................................................2-54
Spurious Vector Generation..............................................................................2-54
Interprocessor Interrupts (IPI)..........................................................................2-55
8259 Compatibility...........................................................................................2-55
Hawk Internal Errror Interrupt..........................................................................2-55
Timers...............................................................................................................2-56
Interrupt Delivery Modes..................................................................................2-56
Block Diagram Description..............................................................................2-57
Program Visible Registers.........................................................................2-59
Interrupt Pending Register (IPR)...............................................................2-59
Interrupt Selector (IS)................................................................................2-59
Interrupt Request Register (IRR)...............................................................2-60
In-Service Register (ISR)..........................................................................2-60
Interrupt Router.........................................................................................2-60
Programming Notes..........................................................................................2-62
External Interrupt Service..........................................................................2-62
Reset State.................................................................................................2-63
Operation..........................................................................................................2-64
Interprocessor Interrupts............................................................................2-64
Dynamically Changing I/O Interrupt Configuration.................................2-64
EOI Register..............................................................................................2-65