IN-1
Index

Numerics

32-Bit Counter 3-73
SMC 3-73
8259 Interrupts 4-3

A

A0-A31 3-4
AACK
as used with PPC Slave 2-7
access timing (ROM) 3-19, 3-20
address
Address Parity Error Address Register
3-72
Address Parity Error Log Register
SMC 3-71
data stepping 2-29
decoders PCI to PPC 2-6
decoders PPC to PCI 2-7
limits on PHB map decoding 2-6
mapping PPC 2-6
modification for little endian transfers
2-40
offsets, as part of map decoders 2-21
parity PPC60x 3-10
pipelining 3-6
transfers 3-9
addressing
mode for PCI Master 2-28
to PCI Slave 2-23
addressing mode
PCI Slave limits 2-24
arbiter
as controlled by the XARB register 2-16
Hawk’s internal 2-34
PPC 2-15, 2-16
arbitration
from PCI Master 2-28
latency 2-29
parking 2-37
architectural overview 2-4
ARTRY_ 3-11

B

big to little endian data swap 2-39
big-endian mode 4-7
bit descriptions 3-38
bit ordering convention
SMC 3-1
block diagram 1-3, 2-3
Hawk SMC 3-3
Hawk used with SDRAM 3-2
block diagrams
Hawk with SDRAMs 3-2
Board Last Reset Register 1-32
bridge
PHB 2-1
PowerPC to PCI Local Bus Bridge 2-1
burst write bandwidth 1-1
Bus Clock Frequency 1-1
bus cycle types
on the PCI bus 2-29
Bus Hog
PPC master device 2-14
bus interface (60x)
to SMC 3-9