Motorola MVME5100 - page 141

Registers
http://www.motorola.com/computer/literature 2-73
2
PPC Arbiter/PCI Arbiter Control Registers
The PPC Arbiter Register (XARB) provides control and status for the PPC
Arbiter. Refer to the section titled PPC Arbiter for more information. The
bits within the XARB register are defined as follows:
FBRx Flatten Burst Read. This field is used by the PPC Arbiter
to control how bus pipelining will be affected after all
burst read cycles. The encoding of this field is shown in
the table below.
FSRx Flatten Single Read. This field is used by the PPC
Arbiter to control how bus pipelining will be affected after
all single beat read cycles. The encoding of this field is
shown in the table below.
FBWx Flatten Burst Write. This field is used by the PPC
Arbiter to control how bus pipelining will be affected after
all burst write cycles. The encoding of this field is shown
in the table below.
FSWx Flatten Single Write. This field is used by the PPC
Arbiter to control how bus pipelining will be affected after
all single beat write cycles. The encoding of this field is
shown in the table below.
Address $FEFF000C
Bit 01234567891
01 11 21 31 41 51 61 71 81 92 02 12 22 32 42 52 62 72 82 93 03 1
Name XARB PARB
FBR1 FBR0 FSR1 FSR0 FBW1 FSW0 FSW1 FSW0 PRI PRK1 PRK0 ENA PRI1 PRI0 PRK3 PRK2 PRK1 PRK0 HIER2 HIER1 HIER0 POL ENA
Operation RW
R
RW RW RW
R R R R R R R R R
R/W R/W R/W R/W R/W R/W R/W
R R
R/W
R
Reset 0
0
0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0
FBR/FSR/FBW/FSW Effects on Bus Pipelining
00 None
01 None
10 Flatten always
11 Flatten if switching masters