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System Memory Controller (SMC)
3
Refresh/Scrub
The SMC performs refresh by doing a burst of 4 CAS-Before-RAS (CBR)
refresh cycles to each block of SDRAM once every 60 microseconds. It
performs scrubs by replacing every 128th refresh burst wit h a read cycle to
8 bytes in each block of SDRAM. If during the read cycle, the SMC detects
a single-bit error, it performs a write cycle back to SDRAM using
corrected data providing the SWEN control bit is set. It does not perform
the write if the SWEN bit is cleared. If the SMC detects a double-bit error,
it does not perform a write.
If so enabled, single- and double-bit scrub errors are logged and the
PPC60x bus master is notified via interrupt.
CSR Accesses
The SMC has a set of control and status registers (CSR) that allow software
to control certain functions and to monitor some status.
External Register Set
The SMC has an external register chip select pin which enables it to talk to
an external set of registers. This interfa ce is like the ROM/Flash interface
but with less flexibility. It is intended fo r the system designer to be able to
implement general-purpose status/control signals with this external set.
Refer to the section on External Register Set, further on in this chapter, for
a description of this register set.
The SMC has a mode in which two of its pins become control register
outputs. When the SMC is to operate in t h is mode, the External Register
Set cannot be implemented. The two control bits appear in the range where
the External Register Set would have been had it been implemented.