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System Memory Controller (SMC)
3
As long as the slave device receives an acknowledge, it will continue to
increment the word address and serially clock out sequential data words.
The I2C sequential read operation is terminated when the I2C master
controller does not respond with an acknowledge. This can be
accomplished by setting only the i2_enbl bit in the I2C Control Register
before receiving the last data word. A stop sequence then must be
transmitted to the slave device by first sett ing the i2_stop and i2_enbl bits
in the I2C Control Register and then writing a dummy data (data=don’t
care) to the I2C Transmitter Data Register. The I2C Status Register must
now be polled to test i2_cmplt bit for the operation-complete status. The
stop sequence will relinquish the ASIC master’s possession of the I2C bus .
Figure 3-9 shows the suggested software flow diagram for programming
the I2C sequential read operation.