xiii
Address Parity Error Log Register............................................................3-71
Address Parity Error Address Register......................................................3-72
32-Bit Counter...........................................................................................3-73
External Register Set.................................................................................3-73
tben Register..............................................................................................3-74
Software Considerations..........................................................................................3-75
Programming ROM/Flash Devices...................................................................3-75
Writing to the Control Registers.......................................................................3-75
Initializing SDRAM Related Control Registers...............................................3-76
SDRAM Speed Attributes.........................................................................3-76
SDRAM Size.............................................................................................3-77
I2C EEPROMs..........................................................................................3-77
SDRAM Base Address and Enable...........................................................3-77
SDRAM Control Registers Initialization Example...................................3-78
Optional Method for Sizing SDRAM........................................................3-84
ECC Codes...............................................................................................................3-87
CHAPTER 4 Hawk Programming Details
Introduction................................................................................................................4-1
PCI Arbitration...........................................................................................................4-1
Hawk MPIC External Interrupts.........................................................................4-1
8259 Interrupts....................................................................................................4-3
Exceptions..................................................................................................................4-5
Sources of Reset..................................................................................................4-5
Soft Reset............................................................................................................4-5
CPU Reset...........................................................................................................4-5
Error Notification and Handling.........................................................................4-6
Endian Issues.............................................................................................................4-7
Processor/Memory Domain................................................................................4-9
MPIC’s Involvement...........................................................................................4-9
PCI Domain........................................................................................................4-9
APPENDIX A Related Documentation
Motorola Computer Group Documents....................................................................A-1
Manufacturers’ Documents.......................................................................................A-2
Related Specifications...............................................................................................A-4