Motorola MVME5100 Processors, Processor Type Identification, Processor PLL Configuration, L2 Cache

System Bus
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Processors
The MVME5100 has the BGA foot print that supports the MPC750,
MPC755 and MPC7410 processors. The maximum external processor bus
speed is 100MHz. Parity checking is supported for the system address and
data busses.
Processor Type Identification
The processor version can be determined by reading the Processor Version
Register (PVR). The PVR version number value for the MPC750 and
MPC755 processors is 0x0008. The processor revision level starts at
0x0100 and is updated for each silicon revision. For example, revis ion 1 of
the MPC750 is 0x00080100. Revision 2 is 0x00080200, and so on.
Incremental revisions, such as 2.1, are identified as 0x00080201 and so on.
For the MPC7410, the PVR version number value is 0x000C, and the
revision levels use the same nomenclature as the MPC750, e.g., 0x0100
and so on.
Processor PLL Configuration
The processor internal clock frequency (core frequency) is a multiple of
the system bus frequency. The processor has four configuration pins,
PLL_CFG[0:3], for hardware strapping of the processor core frequency
between 2x and 8x the system bus frequency, in 0.5x steps.
The PLL configuration is dynamic at power-up and varies depending upon
the existence of a memory mezzanine attached to the host board.
L2 Cache
The MVME5100 SBC uses a back-door L2 cache structure via the Max
processor chip. Max’s L2 cache is implemented with an onchip 2-way , set-
associative tag memory and external direct mapped synchronous SRAMs
for data storage. The external SRAMs are accessed through a dedicated 72-
bit wide (64-bits of data and 8 bits of address) L2 cache port on the
processor. The L2 cache normally operates in copyback modes and
supports system cache coherency through snooping. Parity generation and