xii
Error Logging............................................................................................3-13
ROM/Flash Interface........................................................................................3-14
ROM/Flash Speeds....................................................................................3-19
I2C Interface.....................................................................................................3-22
I2C Byte Write..........................................................................................3-23
I2C Random Read.....................................................................................3-25
I2C Current Address Read........................................................................3-27
I2C Page Write..........................................................................................3-29
I2C Sequential Read..................................................................................3-31
Refresh/Scrub...................................................................................................3-34
CSR Accesses...................................................................................................3-34
External Register Set........................................................................................3-34
Chip Configuration...........................................................................................3-35
Programming Model................................................................................................3-35
CSR Architecture.............................................................................................3-35
Register Summary............................................................................................3-36
Detailed Register Bit Descriptions...................................................................3-38
Vendor/Device Register............................................................................3-39
Revision ID/General Control Register......................................................3-39
SDRAM Enable and Size Register (Blocks A, B, C, D)...........................3-41
SDRAM Base Address Register (Blocks A/B/C/D).................................3-43
CLK Frequency Register...........................................................................3-44
ECC Control Register...............................................................................3-46
Error Logger Register...............................................................................3-50
Error_Address Register.............................................................................3-52
Scrub/Refresh Register..............................................................................3-52
Scrub Address Register.............................................................................3-53
ROM A Base/Size Register.......................................................................3-54
ROM B Base/Size Register.......................................................................3-57
ROM Speed Attributes Registers..............................................................3-59
Data Parity Error Log Register.................................................................3-61
Data Parity Error Address Register...........................................................3-62
Data Parity Error Upper Data Register.....................................................3-62
Data Parity Error Lower Data Register.....................................................3-63
I2C Clock Prescaler Register....................................................................3-64
I2C Control Register.................................................................................3-64
I2C Status Register....................................................................................3-65
I2C Transmitter Data Register..................................................................3-66
I2C Receiver Data Register.......................................................................3-67
SDRAM Enable and Size Register (Blocks E,F,G,H)..............................3-67
SDRAM Base Address Register (Blocks E/F/G/H)..................................3-68
SDRAM Speed Attributes Register..........................................................3-69