Motorola MVME5100 - page 94

2-26 Computer Group Literature Center Web Site

Hawk PCI Host Bridge & Multi-Processor Interrupt Controller

2

PCI FIFO

A 64-bit by 16 entry FIFO (4 cache lines total) is used to hold data between

the PCI Slave and the PPC Master to ensure that optimum data throughput

is maintained. The same FIFO is used for both re ad and write transactions.

A 52-bit by 4 entry FIFO is used to hold command information being

passed between the PCI Slave and the PPC Master. If write posting is

enabled, then the maximum number of transactions that may be posted is

limited by the abilities of either th e data FIFO or the command FIFO. F or

example, one burst transaction, 16 double words long, would make the

data FIFO the limiting factor for write posting. Four single beat

transactions would make the command FIFO be the limiting factor. If

either limit is exceeded then any pending PCI transactions are delayed

(TRDY_ is not asserted) until the PPC Master has completed a portion of

the previously posted transactions and created some room within the

command and/or data FIFOs.

PCI Master

The PCI Master, in conjunction with the c a pabilities of the PPC Slave,

attempts to move data in either single beat or four-beat (burst) transactio ns.

The PCI Master supports 32-bit and 64-bit transactions in the following

manner:

❏All PPC60x single beat transactions, regardless of the byte count,

are subdivided into one or two 32-bit transfers, depending on the

alignment and the size of the transaction. This includes single beat

8-byte transactions.

❏All PPC60x burst transactions are transferred in 64-bit mode if the

PCI bus has 64-bit mode enabled. If at any time during the

transaction the PCI target indicates it can not support 64-bit mode,

the PCI Master continues to transfer the remaining data within that

transaction in 32-bit mode.

The PCI Master can support Critical Word Fir st (CWF) burst transfers.

The PCI Master divides this transaction into two par ts. The first part starts

on the address presented with the CWF transfer request and continues up

to the end of the current cache line. The second transfer starts at the

beginning of the associated cache line and works its way up to (but not

including) the word addressed by the CWF request.

Contents

Main Page Safety Summary Ground the Instrument. Do Not Operate in an Explosive Atmosphere. Keep Away From Live Circuits Inside the Equipment. Use Caution When Exposing or Handling a CRT. ! EMI Caution ! Lithium Battery Caution CE Notice (European Community) Notice Limited and Restricted Rights Legend Contents Page Page Page Page Page Page Page List of Figures Page List of Tables Page Page Page About This Manual Page Page Summary of Changes Overview of Contents Comments and Suggestions Conventions Used in This Manual Terminology Page Page 1Product Data and Memory Maps Table 1-1. MVME Key Features (Continued) Introduction http://www.motorola.com/computer/literature 1-3 The following block diagram illustrates the architecture of the MVME5100 Single Board Computer. Local Bus 33 MHz 32/64-bit PCI VME P2 PCI Expansion Memory maps Processor Memory Map Page Page Page PCI Local Bus Memory Map VMEbus Memory Map System Bus Processors Processor Type Identification Processor PLL Configuration L2 Cache L2 Cache SRAM Size Cache Speed FLASH Memory ECC Memory P2 I/O Modes Serial Presence Detect (SPD) Definitions Hawk ASIC Hawk I2C interface and configuration information Vital Product Data (VPD) and Serial Presence Detect (SPD) Data PCI Local Bus PCI Arbitration Assignments for Hawk ASIC The Ethernet Controller PMC/PCI Expansion Slots The Universe ASIC 1-18 Computer Group Literature Center Web Site Product Data and Memory Maps Figure 1-2. VMEbus Master Mapping VMEBUS PCI MEMORYPROCESSOR PCI Configuration Space Page Hawk External Register Bus Address Assignments Table 1-9. Hawk External Register Bus Summary (Continued) Dual TL16C550 UARTs Status Register MODFAIL Bit Register MODRST Bit Register TBEN Bit Register NVRAM/RTC & Watchdog Timer Software Readable Header/Switch Register (S1) ON ON Geographical Address Register (VME board) Extended Features Register 1 Board Last Reset Register Extended Features Register 2 IPMC7xx ISA Bus Resources W83C554 PIB Registers PC87308VUL Super I/O (ISASIO) Strapping Z85230 ESCC and Z8536 CIO Registers and Port Pins Page Page Page ISA DMA Channels Page 2Hawk PCI Host Bridge & Multi- Processor Interrupt Controller Overview Features Page Block Diagram http://www.motorola.com/computer/literature 2-3 Block Diagram Figure 2-1. Hawk PCI Host Bridge Block Diagram PCI Host Bridge (PHB) PCI Bus PPC60x Bus Functional Description Architectural Overview PPC Bus Interface Page Page Page Page Page Page Page Page Page Page Page Page Page PCI Bus Interface Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Endian Conversion Functional Description http://www.motorola.com/computer/literature 2-39 Page Error Handling Watchdog Timers Page Table 2-14. WDTxCNTL Programming PCI/PPC Contention Handling Page Page Transaction Ordering PHB Hardware Configuration Page Multi-Processor Interrupt Controller (MPIC) MPIC Features: Architecture External Interrupt Interface Page Processors Current Task Priority Nesting of Interrupt Events Spurious Vector Generation Interprocessor Interrupts (IPI) 8259 Compatibility Hawk Internal Errror Interrupt Timers Interrupt Delivery Modes Block Diagram Description Figure 2-9. MPIC Block Diagram Page Page Page Programming Notes Page Operation Page Architectural Notes Effects of Interrupt Serialization Registers PPC Registers The PPC register map of the PHB is shown in Table 2-16. Table 2-16. PPC Register Map for PHB Table 2-16. PPC Register Map for PHB (Continued) Vendor ID/Device ID Registers Registers http://www.motorola.com/computer/literature 2-71 Reset Operation Address $FEFF0008 Bit Page Page Page Page Page Page Page Page Page Page Page Page Page Page If the PSMA or PRTA bit are set, the register is defined by the following table: Page Page Page Page Page Page Page Page Registers http://www.motorola.com/computer/literature 2-95 WDTxSTAT Registers PCI Registers Vendor ID/ Device ID Registers Table 2-18. PCI I/O Register Page Page Revision ID/ Class Code Registers MPIC I/O Base Address Register Page Page Page Page Conceptual perspective from the PCI bus: Perspective from the PPC bus in Big Endian mode: Perspective from the PPC bus in Little Endian mode: Page Perspective from the PPC bus in Big Endian mode: Perspective from the PPC bus in Little Endian mode: MPIC Registers Page Page Feature Reporting Register Page Page Vendor Identification Register Page Spurious Vector Register Page Page Page Timer Destination Registers Page External Source Destination Registers Page Hawk Internal Error Interrupt Destination Register Page Page 3System Memory Controller (SMC) Overview Bit Ordering Convention Features Block Diagrams PPC60x Bus DRAM Synch HAWK Check Data Block Diagrams + + Figure 3-3. Overall SDRAM Connections (4 Blocks using Register Buffers) 3-4 Computer Group Literature Center Web Site HAWK Block Diagrams PPC60x Data MEM Data Figure 3-4. Hawks System Memory Controller Block Diagram http://www.motorola.com/computer/literature 3-5 MEM Addr PPC60x Addr Bus I2C Functional Description SDRAM Accesses Page Page SDRAM Organization PPC60x Bus Interface Page SDRAM ECC 3-12 Computer Group Literature Center Web Site Error Type Single-Beat/Four- Beat Read Single-Beat Write Four-Beat Write Scrub Single-Bit Error Double-Bit Error Triple- (or greater) Bit Error Page ROM/Flash Interface Page Table 3-3. PPC60x to ROM/Flash (16 Bit Width) Address Mapping Table 3-4. PPC60x to ROM/Flash (64 Bit Width) Address Mapping Page Page Table 3-6. PPC60x Bus to ROM/Flash Access Timing (80ns @ 100 MHz) Table 3-7. PPC60x Bus to ROM/Flash Access Timing (50ns @ 100 MHz) Page I2C Interface Page Figure 3-5. Programming Sequence for I2C Byte Write (*) 3-24 Computer Group Literature Center Web Site Page Figure 3-6. Programming Sequence for I2C Random Read 3-26 Computer Group Literature Center Web Site d (*) Page Figure 3-7. Programming Sequence for I2C Current Address Read 3-28 Computer Group Literature Center Web Site (*) Page Figure 3-8. Programming Sequence for I2C Page Write 3-30 Computer Group Literature Center Web Site * ** (*) Page Page Functional Description Figure 3-9. Programming Sequence for I2C Sequential Read http://www.motorola.com/computer/literature 3-33 (*) Refresh/Scrub CSR Accesses External Register Set Chip Configuration Programming Model CSR Architecture 3-36 Computer Group Literature Center Web Site Register Summary Table 3-9 shows a summary of the internal and external register set. Table 3-9. Register Summary Table 3-9. Register Summary (Continued) http://www.motorola.com/computer/literature 3-37 Detailed Register Bit Descriptions http://www.motorola.com/computer/literature 3-39 Vendor/Device Register Page http://www.motorola.com/computer/literature 3-41 SDRAM Enable and Size Register (Blocks A, B, C, D) Page Page Page Page 3-46 Computer Group Literature Center Web Site ECC Control Register Page Page Page Page Page 3-52 Computer Group Literature Center Web Site Error_Address Register Page Page Page Page Page Page http://www.motorola.com/computer/literature 3-59 Page Page Data Parity Error Address Register Data Parity Error Lower Data Register I2C Clock Prescaler Register Page Page http://www.motorola.com/computer/literature 3-67 I2C Receiver Data Register ram h siz2 ram h siz1 ram h siz0 ram h en Page Page Page Page Page 32-Bit Counter Page Software Considerations Programming ROM/Flash Devices Writing to the Control Registers Initializing SDRAM Related Control Registers Page Page Page 3-80 Computer Group Literature Center Web Site Table 3-18. Deriving tras, trp, trcd and trc Control Bit Values from SPD Information (Continued) Page Page Page Page Page Page ECC Codes Table 3-22. Single Bit Errors Ordered by Syndrome Code 4Hawk Programming Details PCI Arbitration Hawk MPIC External Interrupts Page 8259 Interrupts Table 4-2. PBC ISA Interrupt Assignments (Continued) Exceptions Sources of Reset Soft Reset CPU Reset Error Notification and Handling Endian Issues 4-8 Computer Group Literature Center Web Site Hawk Programming Details Figure 4-2. Little-Endian Mode Page Page A ARelated Documentation Motorola Computer Group Documents Manufacturers Documents Table A-2. Manufacturers Documents (Continued) Related Specifications B BMVME5100 VPD Reference Information Vital Product Data (VPD) Introduction How to Read the VPD Information B How to Modify the VPD Information What Happens if the VPD Information is Corrupted? How to Fix Corrupted VPD Information What if Your Board Has the Wrong VPD? How to Fix Wrong VPD Problems B VPD Definitions - Packet Types Table B-1. VPD Packet Types (Continued) Page VPD Definitions - Product Configuration Options Data Table B-2. MCG Product Configuration Options Data (Continued) VPD Definitions - FLASH Memory Configuration Data A product may contain multiple FLASH memory configuration packets. Table B-3. FLASH Memory Configuration Data BVPD Definitions - L2 Cache Configuration Data Table B-4. L2 Cache Configuration Data (Continued) BVPD Definitions - VPD Revision Data Vital Product Data (VPD) Introduction http://www.motorola.com/computer/literature B-13 SROM_CRC.C B-14 Computer Group Literature Center Web Site MVME5100 VPD Reference Information Page B C CVMEbus Mapping Example Page C Page Index Numerics A SMC B C D E F G H I L M N O P Page R Address Parity Error Address S T U V W Z