Programming Model
http://www.motorola.com/computer/literature 3-71
3
swr_dpl swr_dpl causes the SMC to always wait until four clocks after the write command portion of a single write before allowing a precharge to occur. This function may not be required. If such is the case, swr_dpl can be cleared by software.tdp tdp determines the minimum number of clock cycles that the SMC assumes the SDRAM requires to satisfy its Tdp parameter. When tdp is 0, the minimum time provided for Tdp is 1 clock. When tdp is 1, the minimum is 2 clocks.trp trp determines the minimum number of clock cycles that the SMC assumes the SDRAM requires to satisfy its Trp param eter. When trp is 0, the minimum time provided for Trp is 2 clocks. When trp is 1, the minimum is 3 clocks.trcd trcd determines the minimum number of clock cycles that the SMC assumes the SDRAM requires to satisfy its Trcd parameter. When trcd is 0, the minimum time provided for Trcd is 2 clocks. When trcd is 1, the minimum is 3 clocks.Address Parity Error Log Registerapelog apelog is set when a parity error occurs on the PPC60x address bus during any PPC60x address cycle (TS_ asserted to AACK_ asserted). It is cleared by writing a one to it or by power-up re set.ape_tt0-4 ape_tt is the value that was on the TT0-TT4 signals when th e apelog bit was set.
Address $FEF800E0
Bit
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
Name
apelog
0
0
ape_tt0
ape_tt1
ape_tt2
ape_tt3
ape_tt4
0
0
0
0
ape_ap0
ape_ap1
ape_ap2
ape_ap3
0
0
0
0
0
0
0
ape_me
Operation
R/C
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R/W
READ ZERO
Reset
0 P
X
X
0 P
0 P
0 P
0 P
0 P
X
X
X
X
0 P
0 P
0 P
0 P
X
X
X
X
X
X
X
0 PL
X