Motorola MVME5100

Functional Description

http://www.motorola.com/computer/literature 3-25

I2C Random Read

The I2C random read begins in the same manner as the I2C byte write. The

first step in the programming sequence shoul d be to test the i2_cmplt bit

for the operation-complete status. The nex t step is to initiate a start

sequence by first setting the i2_start and i2_enbl bits in the I2C Control

0=0) to the I2C Transmitter Data Register. The i2_cmplt bit will be

automatically clear with the write cycle to th e I2C Transmitter Data

and i2_ackin bits. The i2_cmplt bit becomes set when the device address

and write bit have been transmitted, and the i2_ackin bit provides status as

to whether or not a slave device acknowledged the device address. With

the successful transmission of the device address, the word address will be

loaded into the I2C Transmitter Data Register to be transmitte d to the slave

device. Again, i2_cmplt and i2_ackin bits must be tested for proper

response. At this point, the slave device is still in a write mod e. Therefo re,

another start sequence must be sent to the slave to change the mode to read

by first setting the i2_start and i2_enbl bits in the I2C Control Register and

then writing the device address (bits 7-1) and read bit (bit 0=1) to the I2C

Transmitter Data Register. After i2_cmplt and i2_ackin bits have been

tested for proper response, the I2C master controller writes a dummy value

(data=don’t care) to the I2C Transmitter Data Register.This causes t he I2C

master controller to initiate a read transmiss ion from the slave device.

Again, i2_cmplt bit must be tested for proper response. After the I2C

master controller has received a byte of data (indicated by i2_datin=1 in the

I2C Status Register), the system software ma y then read the data by polling

the I2C Receiver Data Register. The I2C master controller does not

acknowledge the read data for a single byte transmission on the I2C bus,

but must complete the transmission by sending a stop sequence to the slav e

device. This can be accomplished by first setting the i2_stop and i2_enbl

bits in the I2C Control Register and then writing a dummy data (data=don’t

care) to the I2C Transmitter Data Register. The I2C Status Register must

now be polled to test i2_cmplt bit for the operation-complete status. The

stop sequence will relinquish the ASIC master’s possession of the I2C bus .

Figure 3-6 shows the suggested software flow diagram for programming

the I2C random read operation.