Motorola MVME5100 Registers, http://www.motorola.com/computer/literature 2-71, Reset, Operation, Address $FEFF0008 Bit , Name GCSR

Registers
http://www.motorola.com/computer/literature 2-71
2
General Control-Status/Feature Registers
The General Control-Status Register (GCSR) provides miscellaneous
control and status information for the PHB. The bits within the GCSR are
defined as follows:
LEND Endian Select. If set, the PPC bus is operating in little
endian mode. The PPC address is modified as described in
the section titled When PPC Devices are Little Endian on
page 2-39. When LEND is clear, the PPC bus is operating
in Big Endian mode, and all data to/from PCI is swap ped
as described in the section titled When PPC Devices are
Big-Endian on page 2-38.
PFBR PCI Flush Before Read. If set, the PHB guarantees that
all PPC initiated posted write transactions are completed
before any PCI initiated read transactions are allowed to
complete. When PFBR is clear, there is no correlation
between these transaction types and their order of
completion. Refer to the section on Transaction Orderi ng
for more information.
XMBH PPC Master Bus Hog. If set, th e PPC mas ter of the PHB
operates in the Bus Hog mode. Bus Hog mode means the
PPC Master continually requests the PPC bus for the
entire duration of each transfer.
If Bus Hog is not enabled, the PPC master requests the bus
in a normal manner. Refer to the section titled PPC
Master for more information.
Address $FEFF0008
Bit 01234567891
01 11 21 31 41 51 61 71 81 92 02 12 22 32 42 52 62 72 82 93 03 1
Name GCSR
LEND PFBR HMBH XFBR XBT1 XBT0 P64 OPIC XID1 XID0
Operation
R/W R R R R/W R/W R/W R/W R R R R R R R R R R R R R R R R R R R R R R R R
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00