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System Memory Controller (SMC)
3
CLK Frequency Register
CLK FREQUENCY These bits should be programmed with the hexadecimal
value of the operating CLOCK frequency in MHz (i.e.
$42 for 66 MHz). When these bits are programmed this
way, the chip’s prescale counter produces a 1 MHz
(approximate) output. The output of the chip prescale
counter is used by the refresher/scrubber and the 32-bit
counter. After power-up, this register is initialized t o $64
(for 100 MHz). The formula is:
Counter_Output_Frequency = (Clock
Frequency)/CLK_FREQUENCY
For example, if the Clock Frequency is 100 MHz and
CLK_FREQUENCY is $64, then the counter output
frequency is 100 MHz/100 = 1 MHz.
When the CLK pin is operating slower than 100MHz,
software should program CLK_FREQUENCY to be at
least as slow as the CLK pin’s frequency as soon as
possible after power-up reset so that SDRAM refresh does
not get behind.
It is okay for the software then to ta ke some time to “up”
CLK_FREQUENCY to the correct value. Refresh will
get behind only when the actual CLK pin’s frequency is
lower than the value programmed into
CLK_FREQUENCY.
(Note: Hawk 1 and 2 were designed to support SDRAMs
that require a refresh rate of 15.625 us (64 ms / 4096 rows
= 15.625 us). Some SDRAMs require a refresh rate of 7.8
Address $FEF80020
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Name CLK FREQUENCY
drr
0
0
0
0
0
0
0
por
Operation READ/WRITE READ ZERO
R/W
READ ZERO
R
R
R
R
R
R
R
R/C
Reset 64 P X
0-P
X
X
X
X
X
X
X
X
1 P